See Esperanto at DAC 2022!

DAC 2022: the 59th Design Automation Conference

The 2022 Design Automation Conference #DAC #59DAC is in San Francisco, July 10-14.
Learn more about Esperanto Technologies!

  • Hear Craig Cochran of Esperanto Technologies speak in the Intel booth @DAC Tuesday, 7/12 at 11 AM.
  • See Esperanto Technologies' ET-SoC-1 chip featured in the Movellus booth.
  • Hear Bob Brennan of Intel give a tech talk, including Esperanto Technologies, in the DAC Pavilion.

About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community of more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives as well as researchers and academicians from leading universities. Nearly 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area, with approximately 200 of the leading and emerging EDA, silicon, and intellectual property (IP) companies and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design.


See Esperanto at RISC-V Summit 2021

EVENT
Date:

October 20-21, 2021

Venue:

Hyatt Regency Hotel, Santa Clara, CA

Speaker:

Darren Jones, Vice President of VLSI Engineering, Esperanto Technologies


About the Event:

See https://www.linleygroup.com/events/event.php?num=52

About The Linley Group:

See https://www.linleygroup.com/

About Esperanto Technologies:

Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architectur

Uncategorized Event

Esperanto Technologies will speak and exhibit at the Linley Fall Processor Conference, October 20-21, 2021
Title of Talk:

Accelerating ML Workloads with Energy-efficient High Performance RISC-V Processors

Abstract:

Esperanto Technologies has developed the first of a family of accelerator chips for large scale machine learning inference applications. Esperanto’s approach uses over 1000 general-purpose RISC-V cores, each equipped with a vector/tensor unit optimized for common machine learning algorithms and data types. Esperanto’s chip is highly energy-efficient, fully programmable, and adaptable as algorithms change. By leveraging the simplicity of the RISC-V instruction set and carefully designing with low-power techniques, Esperanto’s chip preserves many benefits of general-purpose programming while simultaneously delivering excellent performance and energy efficiency.

Admission is free:

Admission is free to qualified registrants. The conference is intended for chip designers, system designers, equipment vendors, OEM/ODMs, service providers, press, and the financial community. Esperanto is a Gold sponsor of the Linley Fall Processor Conference.


See Esperanto at the Linley Fall Processor Conference 2021

EVENT
Date:

October 20-21, 2021

Venue:

Hyatt Regency Hotel, Santa Clara, CA

Speaker:

Darren Jones, Vice President of VLSI Engineering, Esperanto Technologies


About the Event:

See https://www.linleygroup.com/events/event.php?num=52

About The Linley Group:

See https://www.linleygroup.com/

About Esperanto Technologies:

Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architectur

Uncategorized Event

Esperanto Technologies will speak and exhibit at the Linley Fall Processor Conference, October 20-21, 2021
Title of Talk:

Accelerating ML Workloads with Energy-efficient High Performance RISC-V Processors

Abstract:

Esperanto Technologies has developed the first of a family of accelerator chips for large scale machine learning inference applications. Esperanto’s approach uses over 1000 general-purpose RISC-V cores, each equipped with a vector/tensor unit optimized for common machine learning algorithms and data types. Esperanto’s chip is highly energy-efficient, fully programmable, and adaptable as algorithms change. By leveraging the simplicity of the RISC-V instruction set and carefully designing with low-power techniques, Esperanto’s chip preserves many benefits of general-purpose programming while simultaneously delivering excellent performance and energy efficiency.

Admission is free:

Admission is free to qualified registrants. The conference is intended for chip designers, system designers, equipment vendors, OEM/ODMs, service providers, press, and the financial community. Esperanto is a Gold sponsor of the Linley Fall Processor Conference.


See Esperanto at RISC-V Days Tokyo 2021

Esperanto Technologies Delivers Presentation at RISC-V Days Tokyo 2021

MOUNTAIN VIEW, Calif., October 11, 2021 – Esperanto Technologies™, developer of high-performance, energy-efficient machine learning (ML) inference accelerators based on the RISC-V instruction set, announces its participation in RISC-V Days Tokyo 2021. Esperanto will deliver a presentation at the event.

• Where: Pacifico Yokohama Hotel, and online. Co-located with the ET & IoT 2021 Exhibition (https://www.jasa.or.jp/expo/english/).
• When: November 17-19, 2021, 9: 30-15: 30 JST (Japan Standard Time)
• Presentation: “Accelerating Machine Learning with Energy-efficient, High-performance RISC-V Processors”
• Speaker: Eiji Kasahara of Esperanto Technologies, and BOD member, RISC-V Alliance Japan
• Abstract: What is important for machine learning applications? Energy efficiency, excellent performance, full programmability, and adaptability as algorithms change. Esperanto Technologies solves these challenges with an innovative architecture, leveraging the RISC-V instruction set, and low-power design techniques. Esperanto has developed accelerator chips, and boards, for large scale machine learning inference applications. The SoC uses over 1000 general-purpose RISC-V cores, each equipped with a vector/tensor unit optimized for common machine learning algorithms and data types. Esperanto’s chip, and boards, preserve many benefits of general-purpose programming while simultaneously delivering excellent performance and energy efficiency.

RISC-V Days Tokyo is Japan’s largest RISC-V event, with live and online presentations, exhibition booths, and press conferences. RISC-V Days Tokyo brings together RISC-V-related technology, research, products, and expert engineers, promoting collaboration, technology exchange and business opportunities. Tokyo Day 2020 was held online with 1,053 participants from 11 countries.

The book “Chiselで始めるデジタル回路設計” (Digital Design with Chisel), by Martin Sobert, will be distributed in limited quantities at the venue. A PDF version will also be released.

Esperanto is a Platinum sponsor of RISC-V Days Tokyo 2021.

About RISC-V Days Tokyo 2021:
This event is in collaboration with JASA (Embedded Systems Technology Association), the ET & IoT 2021 Exhibition, RISC-V International (https://riscv.org), and Khronos Group (https://jp.khronos.org). See https://riscv-days-tokyo-2021-autumn.peatix.com/event/3020158/

About Esperanto Technologies:
Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architecture. For more information, please visit esperanto.ai/

 


Dave Ditzel Addresses Accelerating Machine Learning at Hot Chips 33

Hear Dave Ditzel on “Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip”

MOUNTAIN VIEW, Calif., August 1, 2021 – See Esperanto Technologies, developer of high-performance, energy-efficient computing solutions based on RISC-V for Artificial Intelligence (AI), Machine Learning (ML) and Deep Learning (DL) applications, at Hot Chips 33. Dave Ditzel, Chairman and Founder of Esperanto, will speak on accelerating machine learning at Hot Chips in August, 2021.

  • Presentation: “Accelerating ML Recommendation with over a Thousand RISC-V / Tensor Processors on Esperanto’s ET-SoC-1 Chip”
  • When: August 24, 2021 at 8:30AM.
  • Where: Virtual event, online.
  • Agenda: https://www.hotchips.org/advance-program/

Abstract:

Esperanto Technologies has developed an accelerator chip for large scale machine learning inference applications. While many chips for accelerating machine learning have been proposed and built, they often also have various limitations. Some implement solutions highly tailored for convolutional neural networks (CNNs) and other algorithms with fixed-function hardware such as systolic array multipliers but suffer with other ML tasks that don’t exactly match their hardware implemented algorithms. Some only work when the data fits entirely in on-die memory, making them not very suitable for ML recommendation server applications that can require many gigabytes of memory.

Esperanto has taken a different approach, using a large number of general-purpose RISC-V cores, each equipped with a vector/tensor unit optimized for common machine learning algorithms and data types. Esperanto’s chip is highly efficient, fully programmable, and adaptable as algorithms change. By leveraging the simplicity of the RISC-V instruction set and carefully designing with low-power techniques, Esperanto’s chip preserves many benefits of general-purpose programming while simultaneously maintaining excellent energy efficiency.

Esperanto’s low-power design allows multiple ET-SoC-1 chips to be placed on a single PCI Express card delivering many times the throughput of legacy x86, GPU and FPGA solutions, while staying within the power limits of a single accelerator card.

You can download the slides here: Hot Chips Slides 2021

About Hot Chips 2021:

See https://www.hotchips.org/

About Esperanto Technologies:

Esperanto Technologies™ develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon, Barcelona, Spain, and Belgrade, Serbia. For more information, please visit  esperanto.ai/

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Art Swift Delivers Keynote and Speaks on Panel at COOL Chips 24

Art Swift, President and CEO of Esperanto Technologies™, will deliver a keynote and also speak on a panel at COOL Chips 24.

  • When: April 14 and 15 (Japan time.)
  • Where: Virtual event, online.
  • AgendaCOOL Chips www.coolchips.org/2021/advance-program/

Keynote: High-Efficiency Inferencing for Scalable Machine Learning

  • Speaker: Art Swift (Esperanto Technologies)
  • Abstract: The extraordinary market demand for large-scale machine learning solutions requires more than GPUs, FPGAs, or large multiplier arrays. These approaches deliver high performance, but at high costs: high power consumption, prohibitively complicated programming models, and unacceptable inflexibility. Esperanto Technologies CEO Art Swift will describe the architectural approach and design methodology for the company’s first supercomputer-on-chip solution for ML inferencing acceleration. The ET-SoC-1 combines the traditional flexibility and programmability of CPU cores with the high efficiency of autonomous tensor processing to deliver unmatched system-level efficiency and all-layer ML acceleration. Every element of Esperanto’s integrated solution represents best-in-class technology: the simplicity of the RISC-V instruction set, proprietary instruction-set extensions for machine learning, an on-chip mesh interconnect, a uniquely optimized memory hierarchy, state of the art process technology, and custom low-voltage circuits. In this way, Esperanto delivers more performance per watt than existing products without compromising flexibility.
  • When: April 15, 2021 (Japan time)

Panel Discussion: “Hot” Techs for “Cool” AI Computing: Do We have Enough Tricks?

  • Organizer and Moderator: Masato Motomura (Tokyo Tech)
  • Panelists:
    Yusuke Doi (Preferred Networks, Japan)
    Avi Baum (Hailo, Israel)
    Art Swift (Esperanto Technologies, USA)
    Mitsuhisa Sato (Riken, Japan)
  • Abstract: It is often mentioned that data is the new oil in the 21st century. Importantly, oil was able to drive industrial revolution only after the advent of combustion engine. By analogy, data can drive AI revolution only after the right silicon engines, i.e., cool chips. The panel will discuss hot topics regarding this important role that cool chips should fulfill for AI computing from various aspects.
  • When: April 14, 2021 (Japan time)

About COOL Chips 24: See www.coolchips.org/2021/

About Esperanto Technologies:
Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon and Austin, Texas in the United States and multiple sites in Europe. Esperanto has brought together a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications such as AI and Machine Learning. For more information, please visit esperanto.ai/

 

 


Esperanto Technologies to Reveal Chip with 1000+ Cores at RISC-V Summit

PRESS RELEASE

Dec. 1, 2020

About Esperanto Technologies

Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon and Austin, Texas in the United States and multiple sites in Europe. Esperanto has brought together a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications such as AI and Machine Learning. For more information, please visit https://www.esperanto.ai/

About the RISC-V Summit

The third annual RISC-V Summit will highlight the continued rapid expansion of the RISC-V ecosystem, presenting both commercial offerings and exciting open-source developments. Newcomers to RISC-V, as well as the seasoned developers who are interested in broadening their toolsets, are invited to choose from the broad range of tutorials. The comprehensive 100% virtual event will feature keynotes from industry pioneers as well as thought-provoking panel discussions. Network with thought-leaders, technology companies, and researchers spearheading the adoption of this evolutionary change in the silicon market.

All trademarks or registered trademarks are the property of Esperanto Technologies or their respective holders.

Uncategorized Event

Art Swift, CEO of Esperanto Technologies, will present chip that accelerates Machine Learning based on RISC-V ISA

MOUNTAIN VIEW, Calif., Dec. 1, 2020 – Esperanto Technologies™, developer of high-performance, energy-efficient computing solutions based on RISC-V for Artificial Intelligence (AI), Machine Learning (ML) and Deep Learning (DL) applications, will participate in the RISC-V Summit, December 8-10, 2020. Art Swift, CEO of Esperanto, will deliver the presentation: Esperanto Accelerates Machine Learning with 1000+ Low-Power RISC-V Cores on a Single Chip on Tuesday, December 8.

Presentation: Esperanto Accelerates Machine Learning With 1000+ Low-Power RISC-V Cores on a Single Chip

  • Esperanto Technologies has developed a ground-breaking accelerator chip for large-scale machine learning applications employing over 1000 RISC-V cores.
  • In this talk, Esperanto provides an overview of the company’s new ET-SoC-1 chip, which features two kinds of general-purpose 64-bit RISC-V cores. The ET-Maxion, previewed at the RISC-V Summit in 2018, is a superscalar out-of-order core delivering high performance for modern operating systems and applications. The complementary ET-Minion core designed by Esperanto is a leaner, energy efficient, in-order multithreaded core with a vector/tensor accelerator unit at the heart of the massively parallel compute array.
  • The chip’s performance and efficiency is derived from a combination of factors, including the simplicity of the RISC-V instruction set, wide vector/tensor units on every ET-Minion core, a uniquely optimized memory hierarchy, state of the art process technology, and custom pipeline architecture and low-voltage circuits which enables more energy-efficient operation. The result is that Esperanto will deliver better performance per watt than legacy CPU and GPU solutions, as well as competing fixed-function designs without compromising generally purpose flexibility.


2020年11月のRISC-V Day Tokyoでエスペラントの技術をお聞き下さい

カリフォルニア州マウンテンビュー、1030日、2020 –人工知能(AI)、機械学習(ML)、ディープラーニング(DL)アプリケーション向けにRISC-Vベースの高性能でエネルギー効率の高いコンピューティングソリューションを開発しているエスペラント・テクノロジーズ(Esperanto Technologies™)は、2020年11月5-6日に開催される「RISC-V Day Tokyo」の主要スポンサーを務めます。

エスペラントテクノロジーズのプレゼンテーションRISC-V機械学習SoCのためのエスペラントの検証手法

  • 著者エスペラント・テクノロジーズ シニア・テクニカル・リードのShankar Jayaratnam氏とエンジニアリング・ディレクターのRaymond Tang氏。
  • エスペラントは、大規模な機械学習推論アプリケーションのためのRISC-VベースのSoCを開発しました。各汎用RISC-Vコンピュートコアには、機械学習アルゴリズムを高速化するためのベクトル/テンソル処理ユニットが搭載されています。多くのアクティブ並列スレッドがオンチップのメッシュネットワークを介して通信し、エスペラントの命令セット拡張機能がISA検証に複雑な層を追加しました。オープンソースのRISC-V準拠のテストスイートは、最初の一歩となりました。しかし、非常に低い消費電力と非常に高い性能の要件を満たすためには、シリコンが入手可能になる前に、常に進化し続けるAIソフトウェア・スタックで消費電力と性能を予測することは困難でした。これらの問題を解決するために、エスペラントの統一検証プラットフォームは、複数のベンチソースを維持することなく、異なる階層の設計を検証することを可能にしました。このプラットフォームは、機能検証にシミュレーションとエミュレーションを使用し、AIソフトウェア・スタックを直接実行し、SoC全体をMHzの周波数でエミュレートしました。その結果、重要な機能と性能の問題を早期に発見することができ、ソフトウェア・スタックをより迅速に成熟させることができました。エスペラント独自のカバレッジ手法では、ハードウェアとソフトウェアのコ・シミュレーションと仮想プラットフォームを使用して、マイクロアーキテクチャの痕跡を抽出し、テープアウト品質を実現しました。SoCトポロジ全体のコンパイルとシミュレーションには2時間を要し、デバッグのターンアラウンドを迅速に行うことができました。

RISC-V Day Tokyoに参加して、オープンスタンダードのコラボレーションを通じてマイクロプロセッサIP市場を変革する破壊的な力の一部になり、エスペラント技術についてお聞きください。

エスペラント技術について

エスペラント・テクノロジーズは、オープンスタンダードのRISC-V命令セット・アーキテクチャをベースに、人工知能/機械学習のための高性能でエネルギー効率の高いコンピューティング・ソリューションを開発しています。エスペラント社はカリフォルニア州マウンテンビューに本社を置き、米国ではオレゴン州ポートランドとテキサス州オースティンにエンジニアリング拠点があり、ヨーロッパにも複数の拠点があります。詳細は https://old.esperanto.ai/をご覧ください。

RISC-V Day Tokyoについて

RISC-V Day Tokyoは日本最大のRISC-Vイベントです。2020年にはCOVID-19の開催により100%オンライン化されます。RISC-Vエコシステムのメンバーが、IoT、AI、セキュリティ、モバイル、ストレージ、ウェアラブル、オートモーティブなどのアプリケーションにまたがる研究、技術、成果、製品を発表し、コラボレーションと技術交流を行います。RISC-Vは、アーキテクチャへの魅力的なライセンスフリーのアプローチとして、急速に支持を集めています。このオープンスタンダードのコラボレーションは、シリコン市場の確立された秩序を変革し、再構築することになるでしょう。 RISC-Vについての詳細は https://riscv.orgをご覧ください。

Esperanto Technologies Press Contacts for Tokyo Event:

 


Hear Esperanto Technologies at RISC-V Day Tokyo on November 2020

PRESS RELEASE

Oct. 30, 2020

About Esperanto Technologies

Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon and Austin, Texas in the United States and multiple sites in Europe. For more information, please visit https://www.esperanto.ai/

About the RISC-V Day Tokyo

RISC-V Day Tokyo is Japan’s largest RISC-V event. In 2020, it will be 100% online due to COVID-19. RISC-V ecosystem members present their research, technologies, results and products across IoT, AI, security, mobile, storage, wearable, automotive and other applications, for collaboration and technology exchange. RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape the established order of the silicon market. For more about RISC-V, see https://riscv.org.

Esperanto Technologies Press Contacts for Tokyo Event:

Eiji Kasahara, [email protected]
Mike Buchanan, [email protected]
All trademarks or registered trademarks are the property of Esperanto Technologies or their respective holders.

Uncategorized Event

Esperanto Technologies Delivers Presentation on RISC-V Machine Learning SoC Verification

MOUNTAIN VIEW, Calif., Oct. 30, 2020 – Esperanto Technologies™, developer of high-performance, energy-efficient computing solutions based on RISC-V for artificial intelligence (AI), machine learning (ML) and Deep Learning (DL) applications, is a leading sponsor for RISC-V Day Tokyo, November 5-6, 2020. Esperanto will also present a technical paper on verification of its RISC-V based SoC on Friday, November 6.

Esperanto Technologies Presentation: Esperanto’s Verification Methodology for a RISC-V Machine Learning SoC

  • Authors: Shankar Jayaratnam, Senior Technical Lead, and Raymond Tang, Engineering Director, at Esperanto Technologies.
  • Esperanto has developed a RISC-V-based SoC for large scale machine learning inference applications. Each general purpose RISC-V compute core is equipped with a vector/tensor processing unit to accelerate machine learning algorithms. Many active parallel threads communicate over an on-chip mesh network, and Esperanto’s instruction-set extensions added an extra layer of complexity to ISA verification. The open-source RISC-V compliance test suite was a good first step. Yet, to deliver the extremely low power and very high performance requirements, it was challenging to predict power and performance with a constantly evolving AI software stack prior to silicon availability. To solve these problems, Esperanto’s unified verification platform allowed verifying different hierarchies of design without the need to maintain multiple bench sources. This platform used simulation and emulation for functional verification, running the AI software stack directly, and emulating the full SoC at MHz frequencies. As a result, critical functional and performance issues could be identified earlier, allowing the software stack to mature more quickly. Esperanto’s unique coverage methodology used hardware/software co-simulation and virtual platforms to extract micro-architectural traces and achieve tape-out quality. Compiling and simulating the full SoC topology took as little as 2 hours, for fast debug turnaround.

Attend RISC-V Day Tokyo to be part of the disruptive force transforming the microprocessor IP market through open standard collaboration, and hear about Esperanto technology.


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