Esperanto is leading the RISC-V revolution for AI
and enabling a new level of AI performance.

The ET-SoC-1 inference chip is designed to be the world’s highest performance RISC-V commercial chip, delivering a massively parallel, flexible architecture that combines exceptional performance with ultra-low power consumption.

Imagine what you could do with hundreds of
TeraOps of computing performance from the
industry’s most energy-efficient chips for key
AI workloads.

THE ET-SoC-1 INFERENCE CHIP

Designed to be the world’s highest performance
RISC-V commercial chip.

Our high-performance ET-MaxionTM core is designed to deliver high-performance out-of-order single-thread RISC-V execution. Our ET-MinionTM core compute array is designed for energy efficiency while delivering hundreds of TeraOps of computing performance.

The ET-SoC-1 chip features over a thousand
RISC-V processors on a single 7nm chip.

ET-SoC-1 features:

  • 1088 energy-efficient ET-Minion 64-bit RISC-V in-order cores, each with a custom vector/tensor unit optimized for ML applications
  • 4 high-performance ET-Maxion 64-bit RISC-V out-of-order cores for running an OS in self-hosted mode
  • Over 160 million bytes of on-chip SRAM
  • Interfaces for large external memory with low-power LPDDR4x DRAM and eMMC FLASH
  • PCIe Gen4 x8 and other common I/O interfaces

INDUSTRY-LEADING ENERGY EFFICIENCY

Minimum energy consumption across a range
of datacenter inference workloads.

Our approach employs an array of over a thousand of our low-power ET-Minion cores, delivering energy efficiency with high integer and floating-point throughput, including tensor and vector acceleration optimized for ML / DL workloads. Our distributed memory architecture puts on-chip memory where it’s needed, improving processing utilization and relieving memory bandwidth bottlenecks.

The Esperanto ET-Minion
on-chip RISC-V core.

The ET-Minion core, based on the open RISC-V ISA, adds proprietary extensions optimized for machine learning. This general-purpose 64-bit microprocessor executes instructions in order, for maximum efficiency, while extensions support vector and tensor operations on up to 256 bits of floating-point data (using 16-bit or 32-bit operands) or 512 bits of integer data (using 8-bit operands) per clock cycle. Multiply-accumulate operations always work with 32-bit accumulators to avoid loss of precision for large arrays, a real problem for competing products that accumulate to smaller representations. The longest tensor operations execute for 512 cycles without consuming memory bandwidth or power to fetch and decode instructions. These operations are perfectly matched to the execution units; both run at full speed for the full duration of each operation.

The Esperanto ET-Minion
on-chip RISC-V core.

The ET-Minion core, based on the open RISC-V ISA, adds proprietary extensions optimized for machine learning. This general-purpose 64-bit microprocessor executes instructions in order, for maximum efficiency, while extensions support vector and tensor operations on up to 256 bits of floating-point data (using 16-bit or 32-bit operands) or 512 bits of integer data (using 8-bit operands) per clock cycle. Multiply-accumulate operations always work with 32-bit accumulators to avoid loss of precision for large arrays, a real problem for competing products that accumulate to smaller representations. The longest tensor operations execute for 512 cycles without consuming memory bandwidth or power to fetch and decode instructions. These operations are perfectly matched to the execution units; both run at full speed for the full duration of each operation.

The Esperanto ET-Maxion
on-chip RISC-V core.

The ET-Maxion, our custom 64-bit single-thread RISC-V microprocessor core, implements advanced features such as quad issue out-of-order execution, branch prediction, and sophisticated prefetching algorithms to deliver high single-thread performance. It runs the Linux operating system (and others) along with applications. Four ET-Maxion cores are on each chip, along with fully coherent cache memory. ET-Maxion cores are ideal for scheduling tasks across the array of ET-Minion cores, managing data movement and hosting operating systems. In an accelerator configuration, this offloads host processing tasks, delivering better overall system performance per dollar.

High-performance on-chip
interconnect.

Esperanto’s mesh-style network on chip (NoC) was specified to match the requirements of advanced workloads. It distributes operands and results between cores, caches, memory, and I/O. It includes sophisticated debug features so software developers—ours, and yours—can get a high-level view of data movement and simultaneously drill down to uncover and relieve bottlenecks at any point on the network.

On-chip management and
security prevents firmware
corruption.

Even in a hosted configuration, it is useful to have an on-die management processor. Ours, based on an ET-Minion core, connects to an on-die hardware “root-of-trust” subsystem to prevent unauthorized or corrupted firmware updates and ensure you can always track activity inside the chip. These elements communicate through the PCI Express interface or secure local interfaces in both hosted and self-hosted configurations.

Scalable, flexible architecture
for virtually any application.

The Esperanto RISC-V architecture is highly scalable to address different applications, different levels of performance, different power profiles, and varying system form factors. This flexibility delivers optimal energy efficiency for each target application with a family of architecturally consistent products. With over a thousand high-performance, energy-efficient 64-bit RISC-V cores on one chip, the ET-SoC-1 Esperanto can deliver TeraFlops of scalable compute performance.

Software development tools
designed to make programming
a breeze.

Programming sophisticated AI chips is historically difficult and time-consuming. Fortunately, Esperanto has already done the heavy lifting for the major ML frameworks. Building on the RISC-V open-source ecosystem, our host-based software development tools are designed to convert your trained model into an optimized package of code and data that will run efficiently on our architecture.

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THE FUTURE OF COMPUTING INNOVATION

The RISC-V Foundation.

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 2000 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.