

AI solutions that offer outstanding energy efficiency.
We’re using RISC-V to improve TCO for hyperscaler and datacenter customers.

Architecture that scales for any AI workload.
Setting new standards for flexibility and efficiency of AI computing, scalable from cloud to edge.


We’re helping define the future of RISC-V.
We extend the benefits of the RISC-V open source technology.


Esperanto’s new inference chip offers outstanding efficiency for key AI computing workloads.
Meet our new
AI supercomputer on a chip.

We don’t compromise,
so you don’t have to.
We’re committed to delivering outstanding energy efficiency,
performance and scalability.
Our solutions are built on RISC-V, the open instruction set
standard, using an innovative low-power approach which enables us to deliver
an exceptional value proposition for key AI inference applications.
Driven by innovation.

Exceptional energy efficiency for a
full range of key AI workloads.
Power consumption continues to be the most critical problem facing high-performance computing today.
To address this challenge we employ an array of over a thousand low-power ET-MinionTM cores, delivering energy efficiency with high integer and floating-point throughput, including tensor and vector acceleration optimized for ML / DL workloads.

RISC-V is the future of computing innovation.
Esperanto Technologies leverages RISC-V, a free and open ISA enabling a new era of processor innovation through open standards. As a founding member of RISC-V International, Esperanto is at the forefront of the RISC-V revolution, using the instruction set architecture to develop the world’s most efficient parallelized AI accelerators. Our high-performance out-of-order processor cores can boot Linux in self-hosted mode while our energy-efficient multithreaded in-order processor cores form a very powerful compute fabric to accelerate AI and Non-AI workloads. Our software stack supports standard AI frameworks such as GLOW and TVM and leverages the rich RISC-V software ecosystem.

Solutions designed to scale from cloud
to edge AI workloads.
The Esperanto RISC-V architecture can scale to address different applications, different levels of performance, different power profiles, and varying system form factors – while delivering optimal energy efficiency for each target application. With over a thousand high-performance, energy-efficient 64-bit RISC-V cores on our first chip, the ET-SoC-1, Esperanto can deliver TeraFlops of scalable computing performance.

The world’s highest performance
RISC-V commercial chip.
The ET-SoC-1 inference chip is designed to be the world’s highest performance RISC-V commercial chip, with over a thousand RISC-V processors on a single TSMC 7nm chip delivering a massively parallel, flexible architecture that combines exceptional performance and ultra-low power consumption. ET-SoC-1 is now available for evaluation by qualified customers through our Esperanto Access Program.
A leadership team with vision and experience.
Our executive team includes Silicon Valley veterans with deep technology backgrounds who share a commitment to deliver world class computing solutions for the AI industry.

Art Swift
President and CEO
Art has 30 plus years of executive-level experience in the tech and microprocessor industry, including as CEO at low power processor chip maker Transmeta, as president of MIPS, a leading provider of microprocessor IP, as CEO of Wave Computing, a pioneer in dataflow computing architectures, as well as CEO of nanotech innovator Unidym. Previously, Art served in executive-level positions at Cirrus Logic, Digital Equipment’s Alpha processor group, and Sun Microsystems, one of the pioneering companies in networked computing and RISC processing.

Art Swift
President and CEO

Dave Ditzel
Founder, CTO and Board Member
A well-known entrepreneur and visionary in the computer and semiconductor industry, Dave was founder and CEO of Transmeta, maker of low power x86 microprocessors, raising over $600M from startup to a $6B IPO. Dave co-authored “The Case for RISC,” along with professor David Patterson. Previously, Dave was a vice president at Intel Corporation, leading advanced processor projects, and CTO at Sun Microsystems for the SPARC Technology Business. After earning a degree in Electrical Engineering and a separate degree in Computer Science, Dave did his graduate work at U.C. Berkeley under professor David Patterson.

Dave Ditzel
Founder, CTO and Board Member

Udi Kalekin
VP of Software Engineering
Udi brings more than 30 years of experience spanning both technology innovation and business, with a focus on embedded software and software development tools. He has led multi-national software and tools teams in startups as well as established companies. At NXP, Udi headed the compiler and tools team, and later NXP’s advanced automotive many-core architecture and tools technology team. Earlier, he managed a global compiler group at Freescale. Udi served as VP of Software at MIPS Technologies, rebuilding the software team, as well as initiating and driving the Android-on-MIPS effort. Previously, he worked on compiler software at Intel. He was educated at Technion, Israel Institute of Technology in Haifa.

Udi Kalekin
VP of Software Engineering

Lee Flanagin
Chief Business Officer
An experienced marketing, sales, and business development executive, Lee’s industry experience includes AI, semiconductors, IP, cloud, consumer electronics, networking, and storage, spanning startups to Fortune 500 companies. Lee has advised on corporate strategy, marketing, sales, ecosystem partnerships and business development for several AI chip startups focused on datacenter and edge applications. Previously, he was Chief Business Officer / Senior Vice President at Wave Computing; Advisor in the Office of the CTO at Cisco, Head of Worldwide Corporate Communications at SanDisk, Head of Corporate Communications at RAE Systems by Honeywell, and Vice President, Worldwide Corporate Communications at ARC International. Lee received his Bachelor of Arts degree from Michigan State University.

Lee Flanagin
Chief Business Officer

Ralph Harms
Chief Financial Officer
As a high-growth technology company CFO, Ralph has directed finance teams for US, European and Asian pre-IPO and publicly traded companies spanning semiconductors, IoT, enterprise and applications software, IT and telecommunications, and more. His expertise in global financial operations, IPO and merger exits, strategic planning and equity financing helped raise $900M public and $510M venture capital equity, and he has led five IPOs. Ralph attended Stanford University Law School Directors’ College and holds an MBA in Finance from the University of Michigan and a BS EE/CS from Michigan State University.

Ralph Harms
Chief Financial Officer

Darren Jones
VP of VLSI Engineering
Darren has 25 plus years of processor design and verification experience. As VP of Engineering at Wave Computing, he was responsible for the successful tapeout of a novel 16nm CGRA chip for Machine Learning as well as the second generation 7nm design. Prior to that, he held engineering leadership positions at Xilinx, and at MIPS Technologies, driving successful SOC tapeouts and processor IP development. Darren received a BSEE from the University of Illinois and an MSEE from Stanford University. He has co-authored more than 20 patents.

Darren Jones
VP of VLSI Engineering

Jin Kim
Chief Data Scientist
An executive, entrepreneur, and data scientist, Jin’s experience spans enterprise software products and services in AI, big data, and advanced analytics. He has led multinational engineering and marketing teams at both established and startup companies, including GraphSQL, Wave Computing, Objectivity, Skytree, Tom Sawyer Software, Vitria Technology, Tactica, and Trimeter Technologies. Jin’s focus encompasses markets for machine learning and deep learning, data management, integration, analytics and visualization, and mobile and cloud computing. He was the evangelist and technologist behind more than 60 innovative products, from concept to revenue. Jin earned his PhD in Computer Science and Engineering and BS in Electrical Engineering at Carnegie-Mellon University.

Jin Kim
Chief Data Scientist

Bill Orner
VP of Systems and Operations Engineering
Bill Orner has more than 25 years’ experience in professional, consumer and industrial electronics specializing in systems-on-chip, system hardware design, system-on-package, low/ultra-low power electronics, electronic power management, firmware and control systems. Bill joined Esperanto in 2017. Previously, Bill worked at GoPro on the development of custom image processing chips and systems. He has also worked for MIPS, Philips, Transmeta, Portalplayer as well as several startup companies. Mr. Orner has a BSEET from Northeastern University and a MSTM from Pepperdine University. He is a senior member of the IEEE and represents Esperanto for the JEDEC, PCI-SIG and OCP standards groups.

Bill Orner
VP of Systems and Operations Engineering
In quotes.
“Besides announcing its RISC-V plans, Western Digital also disclosed that it had made a strategic investment in Esperanto Technologies, a developer of RISC-V-based SoCs.”
ANTON SHILOV, ANANDTECH
“All in all, Esperanto is moving in the right direction for completing the RISC-V ecosystem. The lower cost and growing selection of RISC-V solutions, coupled with a rapidly growing software ecosystem, represent a real and viable alternative to ARM.”
DAVID SCHOR, WIKICHIP FUZE
“Esperanto exemplifies how members of the RISC-V community are working together to accelerate the wide adoption of the RISC-V architecture, and for expanding our partner and developer ecosystem.”
RICK O'CONNOR, FORMER EXECUTIVE DIRECTOR RISC-V FOUNDATION, NOW CEO OPENHW
“NetSpeed and Esperanto share a similar gene—we are both at the leading edge of what can be done in our respective domains… It is indeed an honor to work with a trailblazing partner like Esperanto.”
SUNDARI MITRA, FORMER CEO NETSPEED, NOW VP INTEL
“Yes, I’ve seen the RISC-V light. Chief protagonist in my conversion was the high priest of microprocessor design himself, Dave Ditzel.”
JIM TURLEY, EE JOURNAL
“The motivation for Esperanto is that there is no RISC-V alternative to high end ARM processors. Without that, it is hard for many companies to make an architectural switch…”
PAUL MCLELLAN, BREAKFAST BYTES BLOG, CADENCE
“With thousands of 64-bit RISC-V cores on one chip, Esperanto will deliver TeraFlops/Watt of scalable computing performance for artificial intelligence, machine learning, and other applications.”
MATHEW DIRJISH, SENSORS ONLINE
“Esperanto is at the leading edge of technology putting thousands of RISC-V cores on a single chip.”