6th RISC-V Workshop Proceedings
The proceedings for the 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017 can be found below. This was our first RISC-V Foundation workshop held outside of North America and as with past workshops, this event was sold out with over 270 registered attendees. Our goals for the workshops are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and to build consensus on the future evolution of the RISC-V instruction set architecture.
This workshop was a four day event broken down as follow:
- Monday May 8, 2017 – Introduction to RISC-V – this day long session was held for those who were new to RISC-V and have yet to be exposed to the RISC-V ISA. The session consisted of presentations from the RISC-V Foundation, some of the original creators of the RISC-V ISA and product presentations from vendors within the RISC-V community.
- Tuesday and Wednesday May 9-10, 2017 – These two days followed our traditional two day format with presentations covering various RISC-V projects underway within the RISC-V community and will included a poster / demo reception on Tuesday evening.
- Thursday May 11, 2017 – The workshop week concluded with RISC-V Foundation meetings with attendance restricted to members of the RISC-V Foundation. The day consisted of Technical and Marketing Committee face to face meetings to progress the work currently underway within our various Task Groups.
Each workshop has helped both document the rapidly rising popularity of RISC-V and boosted it further due to the information shared and collaborations formed at the event.
The 7th RISC-V workshop will be hosted by Western Digital in Milpitas California the week of November 27th, 2017. Save the date and please join us! Registration details and the Call for Papers will be posted later this summer.
6th Workshop Agenda & Proceedings
Monday, May 8th, 2017 Introduction To RISC-V
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Registration and Networking Breakfast | ||
| 9:00am | RISC-V Introduction – Opening Remarks | Rick O’Connor, Executive Director, RISC-V Foundation; Professor Zhigang Mao, Department of Micro/Nano Electronics, Shanghai Jiao Tong University | Video |
| 9:15am | History of Computer Architecture and RISC | Dave Patterson, Pardee Professor of Computer Science, Emeritus, UC Berkeley and author of “Computer Architecture: A Quantitative Approach” | Slides | Video |
| 10:15am | Networking Break | ||
| 10:45am | Why RISC-V? “Instruction Sets Want to be Free” | Krste Asanovic, Professor UC Berkeley, Chairman RISC-V Foundation, Co-Founder SiFive | Slides | Video |
| 11:45am | Introduction to the RISC-V Foundation | Rick O’Connor, Executive Director, RISC-V Foundation | Slides | Video |
| 12:15pm | Morning Session Wrap UP | Rick O’Connor, Executive Director, RISC-V Foundation | |
| 12:30pm | Networking Lunch | ||
| 1:30pm | RISC-V Member Company Introductions | Various RISC-V Foundation Member Companies | Slides | Video |
| 2:15pm | RISC-V Foundation Mini Trade Show | Various RISC-V Foundation Member Companies | |
| 5:00pm | Adjourn for the Day |
Tuesday, May 9th, 2017 6th RISC-V Workshop Day 1
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Registration and Networking Breakfast | ||
| 8:45am | 6th RISC-V Workshop Introduction | Rick O’Connor, RISC-V Foundation | Slides | Video |
| 9:00am | Taking RISC-V to Mainstream ASICs | Charlie Su, Andes Technology | Slides | Video |
| 9:30am | Labeled RISC-V: A New Perspective on Software-Defined Architecture | Zihao Yu, ICT Chinese Academy of Sciences | Slides | Video |
| 10:00am | RISC-V Privileged Architecture | Andrew Waterman, SiFive | Slides | Video |
| 10:30am | Networking Break | ||
| 11:00am | RISC-V Foundation Update | Rick O’Connor, RISC-V Foundation | Slides | Video |
| 11:15am | RISC-V Technical Committee Update | Yunsup Lee, SiFive | Slides | Video |
| 11:30am | RISC-V Marketing Committee Update | Jack Kang, SiFive | Slides | Video |
| 11:45am | Panel Discussion: RISC-V in China | Video | |
| 12:30pm | Networking Lunch | ||
| 1:45pm | Keynote Address: RISC-V at NVIDIA | Frans Sijstermans, NVIDIA | Slides | Video |
| 2:30pm | SCR1 – open-source RISC-V compatible MCU core with support | Ekaterina Berezina, Syntacore | Slides | Video |
| 2:45pm | Making RISC-V IP easy to play with and evaluate | Jack Kang, SiFive | Slides | Video |
| 3:00pm | Automated RISC-V Verification Flow Utilizing Simulation, Formal, and Emulation Technologies | Marcela Zachariasova, Codasip | Slides | Video |
| 3:30pm | Networking Break | ||
| 4:00pm | Reprogrammable Logic in a RISC-V based SoC | Alok Sanghavi, Achronix | Slides | Video |
| 4:30pm | A RISC-V Instruction-set extension for baseband processing applications | Cecil Accetti, Shanghai Jiao Tong University | Slides | Video |
| 4:45pm | Poster / Demo Previews ~ 2min per presenter | Slides | Video | |
| 5:15pm | Transition to Reception | ||
| 5:30pm | Networking Reception, Posters Sessions and Demos | ||
| 9:00pm | Adjourn for the Day |
Wednesday, May 10th, 2017 6th RISC-V Workshop Day 2
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Networking Breakfast | ||
| 9:00am | Dual-core Lockstep Processor using RISC-V Softcores | Sathish Odiga, Microsemi | Slides | Video |
| 9:30am | The 4th lowRISC release: Tagged memory and minion cores | Wei Song, University of Cambridge / lowRISC | Slides | Video |
| 10:00am | Status of the RISC-V Memory Consistency Model | Daniel Lustig, NVIDIA | Slides | Video |
| 10:30am | Networking Break | ||
| 11:00am | Keynote Address: Impedance Matching Expectations Between RISC-V and the Open Hardware Community | Bunnie Huang | Slides | Video |
| 12:00pm | Networking Lunch | ||
| 1:30pm | Panel Discussion: RISC-V Ask Me Anything | Video | |
| 2:15pm | Modern Software Development Methodology for RISC-V Devices | Larry Lapides, Imperas | Slides | Video |
| 2:45pm | RISC-V Debug Updates | Megan Wachs, SiFive | Slides | Video |
| 3:15pm | Networking Break | ||
| 3:45pm | RISC-V Hardware Accelerated Dynamic Binary Translation | Simon Rokicki, IRISA | Slides | Video |
| 4:15pm | 28 Microwatt RV32IMAC | Lauri Koskinen, Minima Processor | Slides | Video |
| 4:30pm | 6th RISC-V Workshop Conclusion | Rick O’Connor, RISC-V Foundation | Video |
| 4:45pm | End of Workshop |
5th RISC-V Workshop Proceedings
Proceedings for the 5th RISC-V Workshop, hosted at Google’s Quad campus in Mountain View, California on November 29-30, 2016 are now available with links to the slide presentations and videos shown in the Agenda below.
The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set.
Each workshop has helped both document the rapidly rising popularity of RISC-V and boosted it further due to the information shared and collaborations formed at the event.
In case you missed the event, here’s some coverage of the workshop to help bring you up to speed:
- EETimes’ Rick Merritt with his full length article covering the event;
- lowRISC’s Alex Bradbury with his live blog for Day 1 and Day 2 of the workshop;
- Cadence’s Paul McLellan with his Breakfast Bytes blog; and
- AB Open’s Gareth Halfacree with his Community Round-Up blog.
Please be sure to join us for the 6th RISC-V Workshop hosted by NVIDIA and Shanghai Jiao Yong University in Shanghai China, May 9th-10th, 2017.
Hope to see you at the next workshop!
5th RISC-V Workshop Proceedings
Tuesday, November 29th, 2016
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Networking Breakfast | ||
| 8:45am | 5th RISC-V Workshop Introduction | Rick O’Connor, RISC-V; Dom Rizzo, Google | Slides | Video |
| 9:00am | RISC-V @ UC San Diego | Michael B. Taylor, UC San Diego | Slides | Video |
| 9:15am | Updates on PULPino | Florian Zaruba, ETH Zurich | Slides | Video |
| 9:30am | SiFive FE300 and low-cost HiFive Development Board | Jack Kang, SiFive | Slides | Video |
| 10:00am | Rapid silicon prototyping and production for RISC-V SoCs | Neil Hand, Codasip | Slides | Video |
| 10:30am | Networking Break | ||
| 11:00am | Extending RISC-V for Application-Specific Requirements | Steve Cox, Synopsys | Slides | Video |
| 11:30am | A memory model for RISC-V | Muralidaran Vijayaraghavan, MIT | Slides | Video |
| 12:00pm | A Memory Consistency Model for RISC-V | Caroline Trippel, Princeton University | Slides | Video |
| 12:30pm | Networking Lunch | ||
| 1:30pm | Keynote Address: Trust, Transparency and Simplicity | Eric Grosse, Google | Slides | Video |
| 2:00pm | RISC-V Foundation Update | Rick O’Connor, RISC-V Foundation | Slides | Video |
| 2:15pm | RISC-V Marketing Committee Update | Arun Thomas, BAE Systems | Slides | Video |
| 2:30pm | RISC-V Technical Committee Update | Yunsup Lee, SiFive | Slides | Video |
| 2:45pm | Rocket Chip Project: a nonprofit foundation for hosting open-source RISC-V implementations, tools, code | Yunsup Lee, SiFive | Slides | Video |
| 3:00pm | Networking Break | ||
| 3:30pm | 128-bit addressing in RISC-V and security | Steve Wallach, Micron | Slides | Video |
| 4:00pm | The Challenges of Securing and Authenticating Embedded Devices and a Suggested Approach for RISC-V | Derek Atkins, SecureRF | Slides | Video |
| 4:15pm | Sanctum: Minimal Hardware Extensions for Strong Software Isolation | Ilia Lebedev, MIT | Slides | Video |
| 4:45pm | Joined up debugging and analysis in the RISC-V world | Gajinder Panesar, UltraSoC | Slides | Video |
| 5:15pm | Poster / Demo Previews ~ 2min per presenter | Slides | Video | |
| 5:45pm | Transition to Reception | ||
| 6:00pm | Networking Reception, Posters Sessions and Demos | Hosted by Google at the Computer History Museum | |
| 9:00pm | Adjourn for the Day |
Wednesday, November 30th, 2016
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Networking Breakfast | ||
| 9:00am | OpenSoC System Architect: An Open Toolkit for Building High Performance SoCs | Farzad Fatollahi-Fard, Lawrence Berkeley National Lab | Slides | Video |
| 9:30am | “V” Vector Extension Proposal | Krste Asanovic, UC Berkeley & SiFive | Slides | Video |
| 10:00am | Towards Thousand-Core RISC-V Shared Memory Systems | Quan Nguyen,MIT | Slides | Video |
| 10:15am | SCRx: a family of state-of-the art RISC-V synthesizable cores | Alexander Redkin, Syntacore | Slides | Video |
| 10:30am | Networking Break | ||
| 11:00am | Enabling hardware/software co-design with RISC-V and LLVM | Alex Bradbury, lowRISC | Slides | Video |
| 11:30am | VM threads: an alternative model for virtual machines on RISC-V | Ron Minnich, Google | Slides | Video |
| 12:00pm | Enabling low-power, smartphone-like graphical UIs for RISC-V SoCs | Michael Gielda, Antmicro | Slides | Video |
| 12:30pm | Networking Lunch | ||
| 1:30pm | A Fast Instruction Set Simulator for RISC-V | Maxim Maslov, Esperanto | Slides | Video |
| 2:00pm | Go on RISC-V | Benjamin Barenblat, Michael Pratt, Google | Slides | Video |
| 2:15pm | A Java Virtual Machine for RISC-V: Porting the Jikes RVM | Martin Maas, UC Berkeley | Slides | Video |
| 2:30pm | YoPuzzle: A mRISC-V development platform for next generations | Elkim Roa, Universidad Industrial de Santander | Slides | Video |
| 2:45pm | RISC-V Community needs Peripheral Cores | Elkim Roa, Universidad Industrial de Santander | Slides | Video |
| 3:00pm | Networking Break | ||
| 3:30pm | Sub-microsecond Adaptive Voltage Scaling in a 28nm RISC-V SoC | Ben Keller, UC Berkeley | Slides | Video |
| 4:00pm | Reprogrammable Redundancy for Cache Vmin Reduction in a 28nm RISC-V Processor | Brian Zimmer, UC Berkeley; NVIDIA | Slides | Video |
| 4:30pm | 5th RISC-V Workshop Conclusion | Rick O’Connor, RISC-V Foundation; Dom Rizzo, Google | Video |
| 4:45pm | End of Workshop |
4th RISC-V Workshop Proceedings
The 4th RISC-V Workshop was hosted at MIT in Cambridge, MA, July 12-13, 2016.
We had tremendous participation with 266 registered attendees representing 63 companies and 42 universities from around the world.
About the Workshop: The goals for our RISC-V workshops are for the community to share information about recent activity in various RISC-V projects underway around the globe, and to build consensus on future steps with the RISC-V ISA. This workshop features talks and poster presentations conveying recent activity in the RISC-V community at large, collected during an open submission period.
The Workshop agenda is shown below together with slides and videos from each of the talks.
3rd RISC-V Workshop Proceedings
3rd RISC-V Workshop Proceedings
The goals of this workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build consensus on future steps with the RISC-V ISA and the launch of the RISC-V Foundation.
This workshop features talks and poster presentations conveying recent activity in the RISC-V community at large, collected during an open submission period.
The Workshop agenda is shown below along with the presentation slides and videos from each talk as well as summaries from each of the Breakout Sessions.
2nd RISC-V Workshop Proceedings
2nd RISC-V Workshop Proceedings
The goals of this workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build consensus on future steps in the RISC-V project, including the RISC-V foundation.
This workshop features talks and poster presentations conveying recent activity in the RISC-V community at large, collected during an open submission period.
See the agenda, along with slides and videos, here.