Uncategorized Event

Esperanto Technologies to Reveal Chip with 1000+ Cores at RISC-V Summit

PRESS RELEASE

Dec. 1, 2020

About Esperanto Technologies

Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon and Austin, Texas in the United States and multiple sites in Europe. Esperanto has brought together a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications such as AI and Machine Learning. For more information, please visit https://www.esperanto.ai/

About the RISC-V Summit

The third annual RISC-V Summit will highlight the continued rapid expansion of the RISC-V ecosystem, presenting both commercial offerings and exciting open-source developments. Newcomers to RISC-V, as well as the seasoned developers who are interested in broadening their toolsets, are invited to choose from the broad range of tutorials. The comprehensive 100% virtual event will feature keynotes from industry pioneers as well as thought-provoking panel discussions. Network with thought-leaders, technology companies, and researchers spearheading the adoption of this evolutionary change in the silicon market.

All trademarks or registered trademarks are the property of Esperanto Technologies or their respective holders.

Uncategorized Event

Art Swift, CEO of Esperanto Technologies, will present chip that accelerates Machine Learning based on RISC-V ISA

MOUNTAIN VIEW, Calif., Dec. 1, 2020 – Esperanto Technologies™, developer of high-performance, energy-efficient computing solutions based on RISC-V for Artificial Intelligence (AI), Machine Learning (ML) and Deep Learning (DL) applications, will participate in the RISC-V Summit, December 8-10, 2020. Art Swift, CEO of Esperanto, will deliver the presentation: Esperanto Accelerates Machine Learning with 1000+ Low-Power RISC-V Cores on a Single Chip on Tuesday, December 8.

• What: RISC-V Summit.
• Where: Virtual event, online.
• When: December 8, 2020.
• Agenda: View the agenda here.
• Register here: https://riscv.informatech.com/2020/registrations/Attendee

Presentation: Esperanto Accelerates Machine Learning With 1000+ Low-Power RISC-V Cores on a Single Chip

• Esperanto Technologies has developed a ground-breaking accelerator chip for large-scale machine learning applications employing over 1000 RISC-V cores.
• In this talk, Esperanto provides an overview of the company’s new ET-SoC-1 chip, which features two kinds of general-purpose 64-bit RISC-V cores. The ET-Maxion, previewed at the RISC-V Summit in 2018, is a superscalar out-of-order core delivering high performance for modern operating systems and applications. The complementary ET-Minion core designed by Esperanto is a leaner, energy efficient, in-order multithreaded core with a vector/tensor accelerator unit at the heart of the massively parallel compute array.
• The chip’s performance and efficiency is derived from a combination of factors, including the simplicity of the RISC-V instruction set, wide vector/tensor units on every ET-Minion core, a uniquely optimized memory hierarchy, state of the art process technology, and custom pipeline architecture and low-voltage circuits which enables more energy-efficient operation. The result is that Esperanto will deliver better performance per watt than legacy CPU and GPU solutions, as well as competing fixed-function designs without compromising generally purpose flexibility.

by Dev Work

2020年11月のRISC-V Day Tokyoでエスペラントの技術をお聞き下さい

カリフォルニア州マウンテンビュー、10月30日、2020年 –人工知能（AI）、機械学習（ML）、ディープラーニング（DL）アプリケーション向けにRISC-Vベースの高性能でエネルギー効率の高いコンピューティングソリューションを開発しているエスペラント・テクノロジーズ（Esperanto Technologies™）は、2020年11月5-6日に開催される「RISC-V Day Tokyo」の主要スポンサーを務めます。

• 会議: RISC-V Day Tokyo
• 会場: 100% オンライン
• 日程: 2020年11月5日～6日 9:00～18:00 (日本時間)
• アジェンダ: View the agenda here. (http://riscv-association.jp/en/riscv-day-tokyo-2020-en/)
• お申し込み(無料)はこちら: https://peatix.com/event/1666430

エスペラントテクノロジーズのプレゼンテーション: RISC-V機械学習SoCのためのエスペラントの検証手法

• 著者: エスペラント・テクノロジーズ シニア・テクニカル・リードのShankar Jayaratnam氏とエンジニアリング・ディレクターのRaymond Tang氏。
• エスペラントは、大規模な機械学習推論アプリケーションのためのRISC-VベースのSoCを開発しました。各汎用RISC-Vコンピュートコアには、機械学習アルゴリズムを高速化するためのベクトル/テンソル処理ユニットが搭載されています。多くのアクティブ並列スレッドがオンチップのメッシュネットワークを介して通信し、エスペラントの命令セット拡張機能がISA検証に複雑な層を追加しました。オープンソースのRISC-V準拠のテストスイートは、最初の一歩となりました。しかし、非常に低い消費電力と非常に高い性能の要件を満たすためには、シリコンが入手可能になる前に、常に進化し続けるAIソフトウェア・スタックで消費電力と性能を予測することは困難でした。これらの問題を解決するために、エスペラントの統一検証プラットフォームは、複数のベンチソースを維持することなく、異なる階層の設計を検証することを可能にしました。このプラットフォームは、機能検証にシミュレーションとエミュレーションを使用し、AIソフトウェア・スタックを直接実行し、SoC全体をMHzの周波数でエミュレートしました。その結果、重要な機能と性能の問題を早期に発見することができ、ソフトウェア・スタックをより迅速に成熟させることができました。エスペラント独自のカバレッジ手法では、ハードウェアとソフトウェアのコ・シミュレーションと仮想プラットフォームを使用して、マイクロアーキテクチャの痕跡を抽出し、テープアウト品質を実現しました。SoCトポロジ全体のコンパイルとシミュレーションには2時間を要し、デバッグのターンアラウンドを迅速に行うことができました。

RISC-V Day Tokyoに参加して、オープンスタンダードのコラボレーションを通じてマイクロプロセッサIP市場を変革する破壊的な力の一部になり、エスペラント技術についてお聞きください。

エスペラント技術について

エスペラント・テクノロジーズは、オープンスタンダードのRISC-V命令セット・アーキテクチャをベースに、人工知能/機械学習のための高性能でエネルギー効率の高いコンピューティング・ソリューションを開発しています。エスペラント社はカリフォルニア州マウンテンビューに本社を置き、米国ではオレゴン州ポートランドとテキサス州オースティンにエンジニアリング拠点があり、ヨーロッパにも複数の拠点があります。詳細は https://old.esperanto.ai/をご覧ください。

RISC-V Day Tokyoについて

RISC-V Day Tokyoは日本最大のRISC-Vイベントです。2020年にはCOVID-19の開催により100%オンライン化されます。RISC-Vエコシステムのメンバーが、IoT、AI、セキュリティ、モバイル、ストレージ、ウェアラブル、オートモーティブなどのアプリケーションにまたがる研究、技術、成果、製品を発表し、コラボレーションと技術交流を行います。RISC-Vは、アーキテクチャへの魅力的なライセンスフリーのアプローチとして、急速に支持を集めています。このオープンスタンダードのコラボレーションは、シリコン市場の確立された秩序を変革し、再構築することになるでしょう。 RISC-Vについての詳細は https://riscv.orgをご覧ください。

Esperanto Technologies Press Contacts for Tokyo Event:

• Eiji Kasahara, [email protected]
• Mike Buchanan, [email protected]

by Holly Stump

Hear Esperanto Technologies at RISC-V Day Tokyo on November 2020

PRESS RELEASE

Oct. 30, 2020

About Esperanto Technologies

Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon and Austin, Texas in the United States and multiple sites in Europe. For more information, please visit https://www.esperanto.ai/

About the RISC-V Day Tokyo

RISC-V Day Tokyo is Japan’s largest RISC-V event. In 2020, it will be 100% online due to COVID-19. RISC-V ecosystem members present their research, technologies, results and products across IoT, AI, security, mobile, storage, wearable, automotive and other applications, for collaboration and technology exchange. RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape the established order of the silicon market. For more about RISC-V, see https://riscv.org.

Esperanto Technologies Press Contacts for Tokyo Event:

Eiji Kasahara, [email protected]
Mike Buchanan, [email protected]
All trademarks or registered trademarks are the property of Esperanto Technologies or their respective holders.

Uncategorized Event

Esperanto Technologies Delivers Presentation on RISC-V Machine Learning SoC Verification

MOUNTAIN VIEW, Calif., Oct. 30, 2020 – Esperanto Technologies™, developer of high-performance, energy-efficient computing solutions based on RISC-V for artificial intelligence (AI), machine learning (ML) and Deep Learning (DL) applications, is a leading sponsor for RISC-V Day Tokyo, November 5-6, 2020. Esperanto will also present a technical paper on verification of its RISC-V based SoC on Friday, November 6.

• What: RISC-V Day Tokyo.
• Where: 100% online.
• When: November 5 − 6, 2020, from 9:00 − 18:00 JST (GMT+9).
• Agenda: View the agenda here.
• Register here: https://peatix.com/event/1666430

Esperanto Technologies Presentation: Esperanto’s Verification Methodology for a RISC-V Machine Learning SoC

• Authors: Shankar Jayaratnam, Senior Technical Lead, and Raymond Tang, Engineering Director, at Esperanto Technologies.
• Esperanto has developed a RISC-V-based SoC for large scale machine learning inference applications. Each general purpose RISC-V compute core is equipped with a vector/tensor processing unit to accelerate machine learning algorithms. Many active parallel threads communicate over an on-chip mesh network, and Esperanto’s instruction-set extensions added an extra layer of complexity to ISA verification. The open-source RISC-V compliance test suite was a good first step. Yet, to deliver the extremely low power and very high performance requirements, it was challenging to predict power and performance with a constantly evolving AI software stack prior to silicon availability. To solve these problems, Esperanto’s unified verification platform allowed verifying different hierarchies of design without the need to maintain multiple bench sources. This platform used simulation and emulation for functional verification, running the AI software stack directly, and emulating the full SoC at MHz frequencies. As a result, critical functional and performance issues could be identified earlier, allowing the software stack to mature more quickly. Esperanto’s unique coverage methodology used hardware/software co-simulation and virtual platforms to extract micro-architectural traces and achieve tape-out quality. Compiling and simulating the full SoC topology took as little as 2 hours, for fast debug turnaround.

Attend RISC-V Day Tokyo to be part of the disruptive force transforming the microprocessor IP market through open standard collaboration, and hear about Esperanto technology.

by Dev Work

Embedded Technologies Expo & Conference 2019

See Esperanto Technologies present on AI, ML & Innovation at the Embedded Technologies Expo & Conference, June 2019

• What: Embedded Technologies Expo & Conference
• When: Wednesday June 26, 2019 2:30pm – 2:55pm
• Where: McEnery Convention Center, San Jose, CA Room 230A
• Presentation: New AI, ML and DL applications are emerging rapidly, with algorithms undergoing fast evolution, revolutionizing architectural choices, a major inflection point, and indicating an accelerating opportunity for RISC-V. Both ML training and inferencing require energy-efficiency with flexible performance vs power tradeoffs. Industry-standard RISC-V ISA: a good baseline from which to build and deliver new, energy-efficient, configurable, scalable, flexible solutions supporting fast algorithmic innovation by designer’s intent on delivering compelling solutions for AI and ML.
• Speaker: Mike Buchanan, Senior Director of Marketing, Esperanto Technologies.
• Track: AI & Machine Learning for Industrial Applications

Learn more.

See the full conference schedule here. 

by Holly Stump

Inaugural RISC-V Summit December 2018

JOIN THE RISC-V REVOLUTION

See Esperanto Technologies at the Inaugural RISC-V Summit, December 2018

Esperanto is sponsoring the RISC-V Summit, will deliver a processor technology paper, and invites you to “Join the RISC-V Revolution!” to be part of the disruptive force transforming the microprocessor IP market through open standard collaboration.

• What: RISC-V Summit.
• Where: Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, California.
• When: Conference and Exhibition Dec. 4-5. Pre-Conference Day Dec. 3. RISC-V Foundation Members Meeting Dec. 6.
• Agenda: View the agenda here.

The RISC-V Summit 2018 will feature an Esperanto exhibit, as well as a technology presentation on a RISC-V based processor design. Please contact [email protected] to set up a meeting.

Presentation: The Esperanto ET-Maxion™ High Performance Out-of-Order RISC-V Processor

• Authors: Polychronis Xekalakis and Chris Celio, CPU Architects at Esperanto Technologies.
• This talk presents an update on ET-Maxion, a high frequency out-of-order RISC-V core which is being designed for TSMC’s 7nm process. It describes the key micro-architectural features that allow ET-Maxion to achieve performance levels comparable to existing commercial high-end processors, and discusses design choices, including shielding against timing attacks such as Spectre and Meltdown, with negligible performance sacrifices. Experiences in implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, along with design challenges, are shared. Finally, a brief overview of support for post-silicon debug and planned performance monitoring improvements for ET-Maxion.
• Read more: See the complete presentation abstract here.

About the RISC-V Summit

The first annual Summit is a major international event promoting RISC-V, bringing together the community for a multi-track conference, tutorials, and exhibits, organized by the RISC-V Foundation, in partnership with Informa’s Knowledge & Networking Division, KNect365. For more information, see https://tmt.knect365.com/risc-v-summit/ For more information about RISC-V (pronounced “risk-five”), please see https://riscv.org.

Learn more.

by Holly Stump

IEEE Micro51 RISC-V Day 2018, Fukuoka, Japan

See Esperanto Technologies at the IEEE Micro51 on RISC-V Day 2018 in Fukuoka, Japan

Esperanto Delivers Presentation on High-Performance ET-Maxion™ RISC-V Core in October 2018

Esperanto will deliver a keynote and technology presentation at the IEEE Micro51 (51st Annual IEEE/ACM International Symposium on Microarchitecture) on RISC-V Day 2018 in Fukuoka, Japan.

• What: IEEE Micro51 on RISC-V Day 2018 Fukuoka
• Where: Grand Hyatt Fukuoka, Fukuoka City, Japan
• When: October 20, 2018
• Agenda: View the agenda here.

IEEE Micro51 will feature an Esperanto keynote and a technology paper on advanced RISC-V processor design. Esperanto invites you to attend, and to contact [email protected] to set up a meeting, or learn more.

Esperanto Keynote: RISC-V, AI and Innovation

• Speaker: Dave Ditzel, President and CEO, Esperanto Technologies
• Emerging AI, ML and DL applications represent a major inflection point that is revolutionizing architectural choices. These applications are growing fast and represent an accelerating opportunity for RISC-V. In ML, both for training and especially for inferencing, energy-efficiency with flexible performance vs power tradeoffs are required. Also, in ML, DL and other AI areas, algorithms are still undergoing rapid change. We believe that to keep from quickly becoming obsolete, that a combination of general purpose RISC-V processors with Domain Specific Accelerators will be a more stable long-term solution than fixed-function accelerators.  Fixed function accelerators, such as a systolic array or data-flow type solutions are unlikely keep up with this fast pace of algorithmic change, and therefore fail to deliver high sustainable performance rates as algorithms change.   We plan to build better solutions based on RISC-V that are configurable, scalable, and support fast algorithmic innovation by designers. RISC-V is a good baseline from which to build and deliver new, energy-efficient, configurable, flexible solutions, based on the industry-standard RISC-V ISA, to deliver compelling solutions for AI and ML.

Esperanto Presentation: Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor

• Authors: Polychronis Xekalakis and Chris Celio, CPU Architects at Esperanto.
• An update on ET-Maxion™, a high frequency out-of-order RISC-V core which is being designed for TSMC’s 7nm process. The talk describes the key micro-architectural features that allow it to achieve performance levels comparable to existing commercial high-end processors and discusses some of the design choices made. One such choice was the design of ET-Maxion as a core shielded against timing attacks such as Spectre and Meltdown, and when such decisions are made early in the design process, they can be supported with negligible performance sacrifices. We will share some of our experiences from implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, and present some of the design challenges encountered. Last, a brief overview of our support for post-silicon debug and the performance monitoring improvements that we are planning to implement for ET-Maxion.

by Holly Stump

Tokyo RISC-V Day October 2018

See Esperanto Technologies at the RISC-V Day Tokyo in October, 2018.

JOIN THE RISC-V REVOLUTION

Esperanto is a Diamond sponsor for the RISC-V Day Tokyo, delivering a keynote and presenting a technical paper on RISC-V based design. We invite you to attend and be part of the disruptive force transforming the microprocessor IP market through open standard collaboration. Please contact [email protected] to set up a meeting.

• What: RISC-V Day Tokyo.
• Where: Fujiwara Hall, Kyosei Building, Keio University, 4-1-1 Hiyoshi, Kohoku-Ku, Yokohama, Kanagawa 223-8526, Japan.
• When: October 18, 2018.
• Agenda: View the agenda here.

Esperanto Keynote: RISC-V, AI and Innovation

• Speaker: Dave Ditzel, President and CEO, Esperanto Technologies
• Emerging AI, ML and DL applications represent a major inflection point that is revolutionizing architectural choices. These applications are growing fast and represent an accelerating opportunity for RISC-V. In ML, both for training and especially for inferencing, energy-efficiency with flexible performance vs power tradeoffs are required. Also, in ML, DL and other AI areas, algorithms are still undergoing rapid change. We believe that to keep from quickly becoming obsolete, that a combination of general purpose RISC-V processors with Domain Specific Accelerators will be a more stable long-term solution than fixed-function accelerators. Fixed function accelerators, such as a systolic array or data-flow type solutions are unlikely keep up with this fast pace of algorithmic change, and therefore fail to deliver high sustainable performance rates as algorithms change.   We plan to build better solutions based on RISC-V that are configurable, scalable, and support fast algorithmic innovation by designers. RISC-V is a good baseline from which to build and deliver new, energy-efficient, configurable, flexible solutions, based on the industry-standard RISC-V ISA, to deliver compelling solutions for AI and ML.

Esperanto Presentation: Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor

• Authors: Polychronis Xekalakis and Chris Celio, CPU Architects at Esperanto.
• An update on ET-Maxion™, a high frequency out-of-order RISC-V core which is being designed for TSMC’s 7nm process. The talk describes the key micro-architectural features that allow it to achieve performance levels comparable to existing commercial high-end processors and discusses some of the design choices made. One such choice was the design of ET-Maxion as a core shielded against timing attacks such as Spectre and Meltdown, and when such decisions are made early in the design process, they can be supported with negligible performance sacrifices. We will share some of our experiences from implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, and present some of the design challenges encountered. Last, a brief overview of our support for post-silicon debug and the performance monitoring improvements that we are planning to implement for ET-Maxion.

Also, each attendee will receive a Japanese edition translation of the “RISC-V Reader.”  Learn more here.

About the RISC-V Day Tokyo

RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape the established world order of the silicon market. The expansive, international RISC-V ecosystem session in Tokyo, organized by the RISC-V Foundation, will explore this disruptive technology, benefits, and commercial implications; discuss current and prospective RISC-V projects and implementations; and influence the future evolution of the instruction set architecture (ISA).  For more information, see https://tmt.knect365.com/risc-v-day-tokyo/.  For more information about RISC-V (pronounced “risk-five”), please see https://riscv.org.

Read more.

by Holly Stump