Valtrix STING DV Platform Selected by AI Chipmaker Esperanto Technologies

PRESS RELEASE

Dec. 5, 2018

About Valtrix Technologies

Valtrix Technologies is an EDA company delivering products and solutions for design verification of CPU, IP and SoC implementations. Headquartered in Bangalore, India, the team comprises of experienced professionals from the semiconductor industry with a common goal to enable verification of complex systems at reduced cost and effort. For more information, please visit http://www.valtrix.in and follow Valtrix on Twitter and LinkedIn.

About Esperanto Technologies

Esperanto TechnologiesTM develops high-performance, energy-efficient computing solutions for AI/ML/DL based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with multiple engineering sites in the US and Europe. Esperanto has brought together a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications such as AI and ML. For more information, please visit www.esperanto.ai and follow Esperanto on twitter and LinkedIn.

Press Releases

To be Used for Design Verification of its 7nm AI Supercomputer-on-Chip

BANGALORE, IndiaDec. 5, 2018 /PRNewswire/ — Valtrix Technologies, an EDA company delivering Design Verification (DV) solutions for the semiconductor industry, announced that Esperanto Technologies has selected Valtrix’s STING DV Platform for design verification of its energy-efficient semiconductor solutions for artificial intelligence (AI) and machine learning (ML) based on the open standard RISC-V instruction set architecture. Esperanto plans to use STING for verifying the architectural compliance and functional correctness of its 7nm AI Supercomputer-on-Chip based on the high-performance ET-Maxion and energy efficient ET-Minion microarchitectures.

“Design verification is a critical aspect for any SoC design, but particularly one with more than a thousand processor cores on a chip,” said Dave Ditzel, president and CEO of Esperanto Technologies. “Esperanto selected STING from Valtrix based on its unique design verification capabilities.  The capabilities of the STING design verification platform, plus Valtrix’s prior experience with RISC-V gave us the additional functionality we were looking for,” continued Ditzel.

Shubhodeep Roy Choudhury, CEO of Valtrix, added: “Esperanto is at the forefront of the RISC-V revolution, developing a leading edge solution for advanced AI/ML applications. We are very proud and excited to be partnering with Esperanto to achieve their mission of developing an AI Supercomputer on a Chip.”

STING, a highly versatile design verification tool developed by Valtrix Technologies, can be used to generate and execute different testing workloads (directed/random/algorithmic) on a device-under-test for verifying architectural compliance and testing its functionalities. The test methodology enables portability of stimulus across simulations, in-circuit emulation, FPGA and silicon resulting into a high degree of verification reuse and efficiency.


Esperanto Technologies at the IEEE Micro51 RISC-V Day in Fukuoka, October 2018

PRESS RELEASE

October 1st, 2018

About Esperanto Technologies

Esperanto Technologies develops high-performance, energy-efficient computing solutions for AI / ML / DL based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon, Austin, Texas, and multiple sites in Europe. Esperanto has brought together a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications such as AI and ML. For more information, please visit www.esperanto.ai and follow Esperanto on twitter and LinkedIn.

All trademarks or registered trademarks are the property of Esperanto Technologies or their respective holders.

Press Releases

Esperanto Delivers Keynote, Presentation on High-Performance ET-Maxion™ RISC-V Core in October 2018

MOUNTAIN VIEW, CALIFORNIA – Esperanto Technologies Inc., developer of high-performance, energy-efficient computing solutions for artificial intelligence (AI) and machine learning (ML) applications based on the open standard RISC-V instruction set architecture, today announced that it will deliver a keynote and technology presentation at the IEEE Micro51 (51st Annual IEEE/ACM International Symposium on Microarchitecture) on RISC-V Day 2018 in Fukuoka, Japan.

IEEE Micro51 will feature an Esperanto keynote and a technology paper on advanced RISC-V processor design. Esperanto invites you to attend, and to contact [email protected] to set up a meeting, or learn more.

Esperanto Keynote: RISC-V, AI and Innovation

  • Speaker: Dave Ditzel, President and CEO, Esperanto Technologies
  • Emerging AI, ML and DL applications represent a major inflection point that is revolutionizing architectural choices. These applications are growing fast and represent an accelerating opportunity for RISC-V. In ML, both for training and especially for inferencing, energy-efficiency with flexible performance vs power tradeoffs are required. Also, in ML, DL and other AI areas, algorithms are still undergoing rapid change. We believe that to keep from quickly becoming obsolete, that a combination of general purpose RISC-V processors with Domain Specific Accelerators will be a more stable long-term solution than fixed-function accelerators.  Fixed function accelerators, such as a systolic array or data-flow type solutions are unlikely keep up with this fast pace of algorithmic change, and therefore fail to deliver high sustainable performance rates as algorithms change.   We plan to build better solutions based on RISC-V that are configurable, scalable, and support fast algorithmic innovation by designers. RISC-V is a good baseline from which to build and deliver new, energy-efficient, configurable, flexible solutions, based on the industry-standard RISC-V ISA, to deliver compelling solutions for AI and ML.

Esperanto Presentation: Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor

  • Authors: Polychronis Xekalakis and Chris Celio, CPU Architects at Esperanto.
  • An update on ET-Maxion™, a high frequency out-of-order RISC-V core which is being designed for TSMC’s 7nm process. The talk describes the key micro-architectural features that allow it to achieve performance levels comparable to existing commercial high-end processors and discusses some of the design choices made. One such choice was the design of ET-Maxion as a core shielded against timing attacks such as Spectre and Meltdown, and when such decisions are made early in the design process, they can be supported with negligible performance sacrifices. We will share some of our experiences from implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, and present some of the design challenges encountered. Last, a brief overview of our support for post-silicon debug and the performance monitoring improvements that we are planning to implement for ET-Maxion.