Esperanto Technologies at the IEEE Micro51 RISC-V Day in Fukuoka, October 2018
PRESS RELEASE
October 1st, 2018
About Esperanto Technologies
Esperanto Technologies develops high-performance, energy-efficient computing solutions for AI / ML / DL based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon, Austin, Texas, and multiple sites in Europe. Esperanto has brought together a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications such as AI and ML. For more information, please visit www.esperanto.ai and follow Esperanto on twitter and LinkedIn.
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Press Releases
Esperanto Delivers Keynote, Presentation on High-Performance ET-Maxion™ RISC-V Core in October 2018
MOUNTAIN VIEW, CALIFORNIA – Esperanto Technologies Inc., developer of high-performance, energy-efficient computing solutions for artificial intelligence (AI) and machine learning (ML) applications based on the open standard RISC-V instruction set architecture, today announced that it will deliver a keynote and technology presentation at the IEEE Micro51 (51st Annual IEEE/ACM International Symposium on Microarchitecture) on RISC-V Day 2018 in Fukuoka, Japan.
- What: IEEE Micro51 on RISC-V Day 2018 Fukuoka
- Where: Grand Hyatt Fukuoka, Fukuoka City, Japan
- When: October 20, 2018
- Agenda: View the agenda here.
IEEE Micro51 will feature an Esperanto keynote and a technology paper on advanced RISC-V processor design. Esperanto invites you to attend, and to contact [email protected] to set up a meeting, or learn more.
Esperanto Keynote: RISC-V, AI and Innovation
- Speaker: Dave Ditzel, President and CEO, Esperanto Technologies
- Emerging AI, ML and DL applications represent a major inflection point that is revolutionizing architectural choices. These applications are growing fast and represent an accelerating opportunity for RISC-V. In ML, both for training and especially for inferencing, energy-efficiency with flexible performance vs power tradeoffs are required. Also, in ML, DL and other AI areas, algorithms are still undergoing rapid change. We believe that to keep from quickly becoming obsolete, that a combination of general purpose RISC-V processors with Domain Specific Accelerators will be a more stable long-term solution than fixed-function accelerators. Fixed function accelerators, such as a systolic array or data-flow type solutions are unlikely keep up with this fast pace of algorithmic change, and therefore fail to deliver high sustainable performance rates as algorithms change. We plan to build better solutions based on RISC-V that are configurable, scalable, and support fast algorithmic innovation by designers. RISC-V is a good baseline from which to build and deliver new, energy-efficient, configurable, flexible solutions, based on the industry-standard RISC-V ISA, to deliver compelling solutions for AI and ML.
Esperanto Presentation: Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor
- Authors: Polychronis Xekalakis and Chris Celio, CPU Architects at Esperanto.
- An update on ET-Maxion™, a high frequency out-of-order RISC-V core which is being designed for TSMC’s 7nm process. The talk describes the key micro-architectural features that allow it to achieve performance levels comparable to existing commercial high-end processors and discusses some of the design choices made. One such choice was the design of ET-Maxion as a core shielded against timing attacks such as Spectre and Meltdown, and when such decisions are made early in the design process, they can be supported with negligible performance sacrifices. We will share some of our experiences from implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, and present some of the design challenges encountered. Last, a brief overview of our support for post-silicon debug and the performance monitoring improvements that we are planning to implement for ET-Maxion.
Esperanto Technologies Plans Energy-Efficient Chips for Artificial Intelligence and Machine Learning, based on the open RISC-V standard
PRESS RELEASE
Nov. 28, 2017
Press Releases
First public technology disclosure from stealth start-up at 7th RISC-V Workshop
MOUNTAIN VIEW, CALIF., Nov. 28, 2017 – Esperanto Technologies president and CEO Dave Ditzel today made the first public disclosure of Esperanto’s development of energy-efficient computing solutions for Artificial Intelligence (AI) and Machine Learning applications based on the open-standard RISC-V Instruction Set Architecture (ISA). During his presentation at the 7th RISC-V Workshop, “Industrial strength high-performance RISC-V processors for energy-efficient computing,” Ditzel unveiled the company’s plans to deliver RISC-V based computing solutions that will achieve both the highest levels of performance and energy-efficiency for artificial intelligence and machine learning applications.
“Esperanto’s goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications which will drive computing innovation for the next decade,” said Ditzel. “By designing in leading-edge 7nm CMOS and with the simplicity of the RISC-V architecture, we can fit over four thousand full 64-bit cores each with vector accelerators on a single chip. By basing our chip on RISC-V we can take advantage of the growing software base of operating systems, compilers and applications. RISC-V is so simple and extensible that we can deliver world class TeraFlop levels of computing without needing to resort to proprietary instruction sets, thereby greatly increasing software availability.”
In his workshop presentation, Ditzel disclosed an overall technology direction for Esperanto’s first System-on-Chip designs, including:
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Artificial Intelligence supercomputer-on-a-chip designed with leading edge 7nm CMOS
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16 “ET-Maxion” 64-bit RISC-V cores for highest single thread performance
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4096 “ET-Minion” energy-efficient RISC-V cores each with vector floating point unit
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Based on the 64-bit open and free RISC-V Instruction Set Architecture
During his talk, Ditzel also noted that in addition to selling its AI supercomputer chip, the company will license its high-performance ET-Maxion and ET-Minion cores to help proliferate the RISC-V architecture.
“There is considerable industry interest in licensing the high-performance and energy-efficient cores we are developing,” noted Ditzel. “As a start-up, we are very focused on addressing our target markets with our AI chip, but we also want to help build the RISC-V ecosystem. We think that by licensing the cores we have in development, we can do both.”
Western Digital’s CTO Martin Fink announced during his keynote speech at the workshop that Western Digital had made a strategic investment in Esperanto. Western Digital’s leadership role in the RISC-V initiative is significant in that it aims to accelerate the advancement of the technology and the surrounding ecosystem by transitioning its own consumption of processors – over one billion cores per year – to RISC-V.
Esperanto’s president and CEO Dave Ditzel is well known for founding and taking public the energy-efficient processor company Transmeta, as well as his leadership work on the SPARC architecture at Sun Microsystems. Earlier in his career, Ditzel helped launch the RISC processor movement of the early 80’s when he co-authored “The Case for the Reduced Instruction Set Computer” with U.C. Berkeley computer science professor David A. Patterson. Before founding Esperanto, Ditzel spent six years at Intel leading various high-performance processor-related projects.
For more information on the RISC-V Foundation and the 7th RISC-V workshop, please visit https://riscv.org/.