MOUNTAIN VIEW, Calif., August 1, 2021 – See Esperanto Technologies, developer of high-performance, energy-efficient computing solutions based on RISC-V for Artificial Intelligence (AI), Machine Learning (ML) and Deep Learning (DL) applications, at Hot Chips 33. Dave Ditzel, Chairman and Founder of Esperanto, will speak on accelerating machine learning at Hot Chips in August, 2021.

• Presentation: “Accelerating ML Recommendation with over a Thousand RISC-V / Tensor Processors on Esperanto’s ET-SoC-1 Chip”
• When: August 24, 2021 at 8:30AM.
• Where: Virtual event, online.
• Agenda: https://www.hotchips.org/advance-program/

Abstract:

Esperanto Technologies has developed an accelerator chip for large scale machine learning inference applications. While many chips for accelerating machine learning have been proposed and built, they often also have various limitations. Some implement solutions highly tailored for convolutional neural networks (CNNs) and other algorithms with fixed-function hardware such as systolic array multipliers but suffer with other ML tasks that don’t exactly match their hardware implemented algorithms. Some only work when the data fits entirely in on-die memory, making them not very suitable for ML recommendation server applications that can require many gigabytes of memory.

Esperanto has taken a different approach, using a large number of general-purpose RISC-V cores, each equipped with a vector/tensor unit optimized for common machine learning algorithms and data types. Esperanto’s chip is highly efficient, fully programmable, and adaptable as algorithms change. By leveraging the simplicity of the RISC-V instruction set and carefully designing with low-power techniques, Esperanto’s chip preserves many benefits of general-purpose programming while simultaneously maintaining excellent energy efficiency.

Esperanto’s low-power design allows multiple ET-SoC-1 chips to be placed on a single PCI Express card delivering many times the throughput of legacy x86, GPU and FPGA solutions, while staying within the power limits of a single accelerator card.

You can download the slides here: Hot Chips Slides 2021

Art Swift, President and CEO of Esperanto Technologies™, will deliver a keynote and also speak on a panel at COOL Chips 24.

• When: April 14 and 15 (Japan time.)
• Where: Virtual event, online.
• Agenda: COOL Chips www.coolchips.org/2021/advance-program/

Keynote: High-Efficiency Inferencing for Scalable Machine Learning

• Speaker: Art Swift (Esperanto Technologies)
• Abstract: The extraordinary market demand for large-scale machine learning solutions requires more than GPUs, FPGAs, or large multiplier arrays. These approaches deliver high performance, but at high costs: high power consumption, prohibitively complicated programming models, and unacceptable inflexibility. Esperanto Technologies CEO Art Swift will describe the architectural approach and design methodology for the company’s first supercomputer-on-chip solution for ML inferencing acceleration. The ET-SoC-1 combines the traditional flexibility and programmability of CPU cores with the high efficiency of autonomous tensor processing to deliver unmatched system-level efficiency and all-layer ML acceleration. Every element of Esperanto’s integrated solution represents best-in-class technology: the simplicity of the RISC-V instruction set, proprietary instruction-set extensions for machine learning, an on-chip mesh interconnect, a uniquely optimized memory hierarchy, state of the art process technology, and custom low-voltage circuits. In this way, Esperanto delivers more performance per watt than existing products without compromising flexibility.
• When: April 15, 2021 (Japan time)

Panel Discussion: “Hot” Techs for “Cool” AI Computing: Do We have Enough Tricks?

• Organizer and Moderator: Masato Motomura (Tokyo Tech)
• Panelists:
  Yusuke Doi (Preferred Networks, Japan)
  Avi Baum (Hailo, Israel)
  Art Swift (Esperanto Technologies, USA)
  Mitsuhisa Sato (Riken, Japan)
• Abstract: It is often mentioned that data is the new oil in the 21st century. Importantly, oil was able to drive industrial revolution only after the advent of combustion engine. By analogy, data can drive AI revolution only after the right silicon engines, i.e., cool chips. The panel will discuss hot topics regarding this important role that cool chips should fulfill for AI computing from various aspects.
• When: April 14, 2021 (Japan time)

About COOL Chips 24: See www.coolchips.org/2021/

MOUNTAIN VIEW, Calif., Dec. 1, 2020 – Esperanto Technologies™, developer of high-performance, energy-efficient computing solutions based on RISC-V for Artificial Intelligence (AI), Machine Learning (ML) and Deep Learning (DL) applications, will participate in the RISC-V Summit, December 8-10, 2020. Art Swift, CEO of Esperanto, will deliver the presentation: Esperanto Accelerates Machine Learning with 1000+ Low-Power RISC-V Cores on a Single Chip on Tuesday, December 8.

• What: RISC-V Summit.
• Where: Virtual event, online.
• When: December 8, 2020.
• Agenda: View the agenda here.
• Register here: https://riscv.informatech.com/2020/registrations/Attendee

Presentation: Esperanto Accelerates Machine Learning With 1000+ Low-Power RISC-V Cores on a Single Chip

• Esperanto Technologies has developed a ground-breaking accelerator chip for large-scale machine learning applications employing over 1000 RISC-V cores.
• In this talk, Esperanto provides an overview of the company’s new ET-SoC-1 chip, which features two kinds of general-purpose 64-bit RISC-V cores. The ET-Maxion, previewed at the RISC-V Summit in 2018, is a superscalar out-of-order core delivering high performance for modern operating systems and applications. The complementary ET-Minion core designed by Esperanto is a leaner, energy efficient, in-order multithreaded core with a vector/tensor accelerator unit at the heart of the massively parallel compute array.
• The chip’s performance and efficiency is derived from a combination of factors, including the simplicity of the RISC-V instruction set, wide vector/tensor units on every ET-Minion core, a uniquely optimized memory hierarchy, state of the art process technology, and custom pipeline architecture and low-voltage circuits which enables more energy-efficient operation. The result is that Esperanto will deliver better performance per watt than legacy CPU and GPU solutions, as well as competing fixed-function designs without compromising generally purpose flexibility.

カリフォルニア州マウンテンビュー、10月30日、2020年 –人工知能（AI）、機械学習（ML）、ディープラーニング（DL）アプリケーション向けにRISC-Vベースの高性能でエネルギー効率の高いコンピューティングソリューションを開発しているエスペラント・テクノロジーズ（Esperanto Technologies™）は、2020年11月5-6日に開催される「RISC-V Day Tokyo」の主要スポンサーを務めます。

• 会議: RISC-V Day Tokyo
• 会場: 100% オンライン
• 日程: 2020年11月5日～6日 9:00～18:00 (日本時間)
• アジェンダ: View the agenda here. (http://riscv-association.jp/en/riscv-day-tokyo-2020-en/)
• お申し込み(無料)はこちら: https://peatix.com/event/1666430

エスペラントテクノロジーズのプレゼンテーション: RISC-V機械学習SoCのためのエスペラントの検証手法

• 著者: エスペラント・テクノロジーズ シニア・テクニカル・リードのShankar Jayaratnam氏とエンジニアリング・ディレクターのRaymond Tang氏。
• エスペラントは、大規模な機械学習推論アプリケーションのためのRISC-VベースのSoCを開発しました。各汎用RISC-Vコンピュートコアには、機械学習アルゴリズムを高速化するためのベクトル/テンソル処理ユニットが搭載されています。多くのアクティブ並列スレッドがオンチップのメッシュネットワークを介して通信し、エスペラントの命令セット拡張機能がISA検証に複雑な層を追加しました。オープンソースのRISC-V準拠のテストスイートは、最初の一歩となりました。しかし、非常に低い消費電力と非常に高い性能の要件を満たすためには、シリコンが入手可能になる前に、常に進化し続けるAIソフトウェア・スタックで消費電力と性能を予測することは困難でした。これらの問題を解決するために、エスペラントの統一検証プラットフォームは、複数のベンチソースを維持することなく、異なる階層の設計を検証することを可能にしました。このプラットフォームは、機能検証にシミュレーションとエミュレーションを使用し、AIソフトウェア・スタックを直接実行し、SoC全体をMHzの周波数でエミュレートしました。その結果、重要な機能と性能の問題を早期に発見することができ、ソフトウェア・スタックをより迅速に成熟させることができました。エスペラント独自のカバレッジ手法では、ハードウェアとソフトウェアのコ・シミュレーションと仮想プラットフォームを使用して、マイクロアーキテクチャの痕跡を抽出し、テープアウト品質を実現しました。SoCトポロジ全体のコンパイルとシミュレーションには2時間を要し、デバッグのターンアラウンドを迅速に行うことができました。

RISC-V Day Tokyoに参加して、オープンスタンダードのコラボレーションを通じてマイクロプロセッサIP市場を変革する破壊的な力の一部になり、エスペラント技術についてお聞きください。

MOUNTAIN VIEW, Calif., Oct. 30, 2020 – Esperanto Technologies™, developer of high-performance, energy-efficient computing solutions based on RISC-V for artificial intelligence (AI), machine learning (ML) and Deep Learning (DL) applications, is a leading sponsor for RISC-V Day Tokyo, November 5-6, 2020. Esperanto will also present a technical paper on verification of its RISC-V based SoC on Friday, November 6.

• What: RISC-V Day Tokyo.
• Where: 100% online.
• When: November 5 − 6, 2020, from 9:00 − 18:00 JST (GMT+9).
• Agenda: View the agenda here.
• Register here: https://peatix.com/event/1666430

Esperanto Technologies Presentation: Esperanto’s Verification Methodology for a RISC-V Machine Learning SoC

• Authors: Shankar Jayaratnam, Senior Technical Lead, and Raymond Tang, Engineering Director, at Esperanto Technologies.
• Esperanto has developed a RISC-V-based SoC for large scale machine learning inference applications. Each general purpose RISC-V compute core is equipped with a vector/tensor processing unit to accelerate machine learning algorithms. Many active parallel threads communicate over an on-chip mesh network, and Esperanto’s instruction-set extensions added an extra layer of complexity to ISA verification. The open-source RISC-V compliance test suite was a good first step. Yet, to deliver the extremely low power and very high performance requirements, it was challenging to predict power and performance with a constantly evolving AI software stack prior to silicon availability. To solve these problems, Esperanto’s unified verification platform allowed verifying different hierarchies of design without the need to maintain multiple bench sources. This platform used simulation and emulation for functional verification, running the AI software stack directly, and emulating the full SoC at MHz frequencies. As a result, critical functional and performance issues could be identified earlier, allowing the software stack to mature more quickly. Esperanto’s unique coverage methodology used hardware/software co-simulation and virtual platforms to extract micro-architectural traces and achieve tape-out quality. Compiling and simulating the full SoC topology took as little as 2 hours, for fast debug turnaround.

Attend RISC-V Day Tokyo to be part of the disruptive force transforming the microprocessor IP market through open standard collaboration, and hear about Esperanto technology.

BANGALORE, India, Dec. 5, 2018 /PRNewswire/ — Valtrix Technologies, an EDA company delivering Design Verification (DV) solutions for the semiconductor industry, announced that Esperanto Technologies has selected Valtrix’s STING DV Platform for design verification of its energy-efficient semiconductor solutions for artificial intelligence (AI) and machine learning (ML) based on the open standard RISC-V instruction set architecture. Esperanto plans to use STING for verifying the architectural compliance and functional correctness of its 7nm AI Supercomputer-on-Chip based on the high-performance ET-Maxion and energy efficient ET-Minion microarchitectures.

“Design verification is a critical aspect for any SoC design, but particularly one with more than a thousand processor cores on a chip,” said Dave Ditzel, president and CEO of Esperanto Technologies. “Esperanto selected STING from Valtrix based on its unique design verification capabilities.  The capabilities of the STING design verification platform, plus Valtrix’s prior experience with RISC-V gave us the additional functionality we were looking for,” continued Ditzel.

Shubhodeep Roy Choudhury, CEO of Valtrix, added: “Esperanto is at the forefront of the RISC-V revolution, developing a leading edge solution for advanced AI/ML applications. We are very proud and excited to be partnering with Esperanto to achieve their mission of developing an AI Supercomputer on a Chip.”

STING, a highly versatile design verification tool developed by Valtrix Technologies, can be used to generate and execute different testing workloads (directed/random/algorithmic) on a device-under-test for verifying architectural compliance and testing its functionalities. The test methodology enables portability of stimulus across simulations, in-circuit emulation, FPGA and silicon resulting into a high degree of verification reuse and efficiency.