Securing High-performance RISC-V Processors from Time Speculation @RISC-V Barcelona Workshop

Christopher Celio and Jose Renau, CPU Architects from Esperanto Technologies, discussed potential changes to future high-performance RISC-V processors intended to eliminate speculation-based timing attacks, such as Spectre and Meltdown. They presented a proposal for RISC-V cores which minimizes changes to the RISC-V ISA or platform specifications in order to provide security against timing-based attacks.

2018-08-01T04:32:09+00:00May 24th, 2018|