Tokyo RISC-V Day October 2018
See Esperanto Technologies at the RISC-V Day Tokyo in October, 2018.
JOIN THE RISC-V REVOLUTION
Esperanto is a Diamond sponsor for the RISC-V Day Tokyo, delivering a keynote and presenting a technical paper on RISC-V based design. We invite you to attend and be part of the disruptive force transforming the microprocessor IP market through open standard collaboration. Please contact [email protected] to set up a meeting.
- What: RISC-V Day Tokyo.
- Where: Fujiwara Hall, Kyosei Building, Keio University, 4-1-1 Hiyoshi, Kohoku-Ku, Yokohama, Kanagawa 223-8526, Japan.
- When: October 18, 2018.
- Agenda: View the agenda here.
Esperanto Keynote: RISC-V, AI and Innovation
- Speaker: Dave Ditzel, President and CEO, Esperanto Technologies
- Emerging AI, ML and DL applications represent a major inflection point that is revolutionizing architectural choices. These applications are growing fast and represent an accelerating opportunity for RISC-V. In ML, both for training and especially for inferencing, energy-efficiency with flexible performance vs power tradeoffs are required. Also, in ML, DL and other AI areas, algorithms are still undergoing rapid change. We believe that to keep from quickly becoming obsolete, that a combination of general purpose RISC-V processors with Domain Specific Accelerators will be a more stable long-term solution than fixed-function accelerators. Fixed function accelerators, such as a systolic array or data-flow type solutions are unlikely keep up with this fast pace of algorithmic change, and therefore fail to deliver high sustainable performance rates as algorithms change. We plan to build better solutions based on RISC-V that are configurable, scalable, and support fast algorithmic innovation by designers. RISC-V is a good baseline from which to build and deliver new, energy-efficient, configurable, flexible solutions, based on the industry-standard RISC-V ISA, to deliver compelling solutions for AI and ML.
Esperanto Presentation: Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor
- Authors: Polychronis Xekalakis and Chris Celio, CPU Architects at Esperanto.
- An update on ET-Maxion™, a high frequency out-of-order RISC-V core which is being designed for TSMC’s 7nm process. The talk describes the key micro-architectural features that allow it to achieve performance levels comparable to existing commercial high-end processors and discusses some of the design choices made. One such choice was the design of ET-Maxion as a core shielded against timing attacks such as Spectre and Meltdown, and when such decisions are made early in the design process, they can be supported with negligible performance sacrifices. We will share some of our experiences from implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, and present some of the design challenges encountered. Last, a brief overview of our support for post-silicon debug and the performance monitoring improvements that we are planning to implement for ET-Maxion.
Also, each attendee will receive a Japanese edition translation of the “RISC-V Reader.” Learn more here.
About the RISC-V Day Tokyo
RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape the established world order of the silicon market. The expansive, international RISC-V ecosystem session in Tokyo, organized by the RISC-V Foundation, will explore this disruptive technology, benefits, and commercial implications; discuss current and prospective RISC-V projects and implementations; and influence the future evolution of the instruction set architecture (ISA). For more information, see https://tmt.knect365.com/risc-v-day-tokyo/. For more information about RISC-V (pronounced “risk-five”), please see https://riscv.org.
