Oct. 30, 2020

About Esperanto Technologies

Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon and Austin, Texas in the United States and multiple sites in Europe. For more information, please visit

About the RISC-V Day Tokyo

RISC-V Day Tokyo is Japan’s largest RISC-V event. In 2020, it will be 100% online due to COVID-19. RISC-V ecosystem members present their research, technologies, results and products across IoT, AI, security, mobile, storage, wearable, automotive and other applications, for collaboration and technology exchange. RISC-V is fast gaining support as an attractive license-free approach to architecture. This open standard collaboration will transform and reshape the established order of the silicon market. For more about RISC-V, see

Esperanto Technologies Press Contacts for Tokyo Event:

Eiji Kasahara, [email protected]
Mike Buchanan, [email protected]
All trademarks or registered trademarks are the property of Esperanto Technologies or their respective holders.

Hear Esperanto Technologies at RISC-V Day Tokyo on November 2020

Esperanto Technologies Delivers Presentation on RISC-V Machine Learning SoC Verification

MOUNTAIN VIEW, Calif., Oct. 30, 2020 – Esperanto Technologies™, developer of high-performance, energy-efficient computing solutions based on RISC-V for artificial intelligence (AI), machine learning (ML) and Deep Learning (DL) applications, is a leading sponsor for RISC-V Day Tokyo, November 5-6, 2020. Esperanto will also present a technical paper on verification of its RISC-V based SoC on Friday, November 6.

Esperanto Technologies Presentation: Esperanto’s Verification Methodology for a RISC-V Machine Learning SoC

  • Authors: Shankar Jayaratnam, Senior Technical Lead, and Raymond Tang, Engineering Director, at Esperanto Technologies.
  • Esperanto has developed a RISC-V-based SoC for large scale machine learning inference applications. Each general purpose RISC-V compute core is equipped with a vector/tensor processing unit to accelerate machine learning algorithms. Many active parallel threads communicate over an on-chip mesh network, and Esperanto’s instruction-set extensions added an extra layer of complexity to ISA verification. The open-source RISC-V compliance test suite was a good first step. Yet, to deliver the extremely low power and very high performance requirements, it was challenging to predict power and performance with a constantly evolving AI software stack prior to silicon availability. To solve these problems, Esperanto’s unified verification platform allowed verifying different hierarchies of design without the need to maintain multiple bench sources. This platform used simulation and emulation for functional verification, running the AI software stack directly, and emulating the full SoC at MHz frequencies. As a result, critical functional and performance issues could be identified earlier, allowing the software stack to mature more quickly. Esperanto’s unique coverage methodology used hardware/software co-simulation and virtual platforms to extract micro-architectural traces and achieve tape-out quality. Compiling and simulating the full SoC topology took as little as 2 hours, for fast debug turnaround.

Attend RISC-V Day Tokyo to be part of the disruptive force transforming the microprocessor IP market through open standard collaboration, and hear about Esperanto technology.