RISC-V Workshop in Chennai Proceedings

The RISC-V Workshop in Chennai, India took place July 18-19, 2018.

Hosted by The Indian Institute of Technology Madras (IIT Madras) and sponsored by Western Digital, the RISC-V Workshop in Chennai discussed current and prospective RISC-V projects and implementations to influence the future evolution of the instruction set architecture (ISA) from Silicon Valley to Silicon Fenn and beyond.

The event featured in-depth technical presentations and updates on the RISC-V architecture, a speaking lineup from leading technology companies and research institutions in the RISC-V ecosystem, opportunities for networking and a demo zone showing the latest innovations in the market.


Check out the slides and videos from each of the sessions here.