Second Workshop on Computer Architecture Research with RISC-V (CARRV 2018)
May 28, 2018
|By Holly Stump
The Second Workshop on Computer Architecture Research with RISC-V (CARRV) brings together researchers in fields related to computer architecture, compilers, and systems for technical exchange on using RISC-V in computer architecture research. It feastured the paper:
- Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud
- By Donggyu Kim (University of California, Berkeley), Christopher Celio (Esperanto Technologies), Sagar Karandikar (University of California, Berkeley), David Biancolin (University of California, Berkeley), Jonathan Bachrach (University of California, Berkeley), Krste Asanovic (University of California, Berkeley) [paper]
