Why RISC-V?
RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom, paving the way for the next 50 years of computing design and innovation.
Unlike legacy Instruction Set Architectures such as ARM or x86, RISC-V does not carry the baggage of the past. Instead, the ISA is clean-slate design based on decades of RISC research and use. It reflects the philosophy of simplicity and elegance – an ISA that fits on a single sheet of paper instead of thousands of pages in an architecture manual. Furthermore, the RISC-V ISA provides the ability for users to extend the instruction set both in terms of optional user-defined extensions and community-driven extensions such as Vector instructions and Security.
The simplicity and elegance of the RISC-V Instruction result in SoC designs that are simpler, have fewer logic gates, consume less energy, and ultimately cost less. In a design targeted for the IoT, this enables extremely low cost, very efficient designs. For high-end applications, the simplicity of RISC-V results in the potential for higher clock speeds, exceptional overall performance and for standout efficiency in terms of Operations per Watt.
With more than seventy companies and organizations using RISC-V to innovate in processors, SoC designs, and development tools, the ISA is rapidly becoming the “innovation platform of choice.” Growing out of academic roots, the ISA is now being embodied in dozens of chip designs ranging across the performance spectrum. As the innovation continues over the next several years, RISC-V adopters will launch SoC devices that rival the performance of any x86- or ARM-based devices while being substantially better in terms of energy efficiency. New features, extensions and cores are being developed at a rapid rate.
In parallel with chip development on the RISC-V ISA, there has been a commensurate growth in development tools and ecosystem support. New tools and development techniques that don’t exist for other ISA’s are also already in use on RISC-V based designs. While the owners of legacy architectures can argue that they have mature ecosystems, RISC-V will be rapidly catching up based on the strength of the community effort. Already, the RISC-V open ISA has support from a broad range of operating systems, software vendors and tool developers.
Further evidence for the momentum of RISC-V can be seen it the growth of the RISC-V foundation. Founded in 2015, the foundation has rapidly grown to include more than 70 member companies and organizations. The bi-annual RISC-V workshops have grown from small academic conferences to standing room only major events which are over-subscribed both in terms of attendance but also in terms of technical papers submitted. In Asia, and in greater China in particular, the level of interest is beyond all expectations as there is a keen desire to escape the monopolistic practices of the existing owners of the leading ISAs. The excitement and enthusiasm are palpable and is reminiscent of the early days of the open source Linux operating system.
Given this backdrop of momentum, enthusiasm and innovation, it seems certain that the open RISC-V ISA has the potential to become the Instruction Set of choice for the new demanding applications of the connected world. Old legacy applications and ISA’s will of course remain, but over time will be supplanted by RISC-V.
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