In Semiconductor Engineering, by Brian Bailey: The Challenge Of RISC-V Compliance.

“Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.”

With commentary by Allen Baum, system architect at Esperanto Technologies and chair of the RISC-V Compliance Task Group.

  • “RISC-V is an open-source standard ISA with exceptional modularity and extensibility,” says Allen Baum, system architect at Esperanto Technologies and chair of the RISC-V Compliance Task Group. “Anyone can build an implementation and there are no license fees, except for commercial use of the trademarks. A basic instruction set is augmented by extensions to support special functions such as atomic and compressed instructions, and additional data types such as floating point, vector and bit operations.”
  • “The potential success of RISC-V isn’t simply that the architecture is open, but that any implementation can run applications and system software written for the ISA. “Implementers are free to add custom extensions to boost capabilities and performance, while at the same time don’t have to include features that aren’t needed,” adds Baum. “Unconstrained flexibility, however, can lead to incompatibilities that could fragment the customer base and eliminate the incentives for cooperative ecosystem development.”
  • “The RISC-V Foundation and its Compliance Working Group are developing and maintaining test suites, framework and methodology to enable its ecosystem to ensure ISA compatible processors meet the demand of the software user base for RISC-V. “The RISC-V compliance framework has three major elements,” says Esperanto’s Baum. “A modular set of test suites that exercise all aspects of the ISA; golden reference signatures that define correct execution results; and frameworks that select and configure appropriate test suites based on both platform requirements and claimed device capabilities, run the tests and compare the results with reference signatures, reporting success or failure.”