RISC-V Cores: SweRV and ET-Maxion

Read Paul McLellan’s blog on two new RISC-V based cores, including Esperanto’s Maxion!

Highlights:

“Esperanto’s Polychronis Xekalakis gave a “sneak preview” of the ET-Maxion and how they went about building it. First, a summary of Maxion:

  • High-frequency design operation at 2+ GHz designed for TSMC 7nm (they feel the frequency can go higher)
  • 10 stages from fetch to write-back for 1-cycle ALU op: 4-stage fetch, 2-cycle allocate and rename, 2-cycle dispatch and read PRF, 1 cycle execute, and 1 cycle write back
  • Fetch and decode: 48 entry iTLB, banked 32KB iCache, 2K entry compressed BTB, state-of-the-art conditional predictor with separate path-based indirect predictor
  • OoO and execution: 64 entry distributed scheduler, 128 entry reorder buffer, 32 entry load queue, 32 entry store queue, 8R/4W 128 entry iPRF, 3R/2W 64 fPRF, 1 load/store, 2 simple ALU, 2 complex ALU/branch
  • Memory: 32 entry dTLB and 1K entry unified L2 TLB, fully coherent 64KB data cache and unified 4MB L2 cache, aggressive stride prefetchers for L1 and L2 data caches
  • RISC-V ISA: support for compressed ISA, privileged ISA, fully respects the relaxed consistency model, supports external debug spec”
2019-01-16T18:33:21+00:00