Securing High-performance RISC-V Processors from Time Speculation @ RISC-V Barcelona Workshop
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May 24th, 2018
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Christopher Celio and Jose Renau, CPU Architects from Esperanto Technologies, discussed potential changes to future high-performance RISC-V processors intended to eliminate speculation-based timing attacks, such as Spectre and Meltdown. They presented a proposal for RISC-V cores which minimizes changes to the RISC-V ISA or platform specifications in order to provide security against timing-based attacks.
Admission is free:
Admission is free to qualified registrants. The conference is intended for chip designers, system designers, equipment vendors, OEM/ODMs, service providers, press, and the financial community. Esperanto is a Gold sponsor of the Linley Fall Processor Conference.
Privileged ISA Tutorial @RISC-V Barcelona Workshop
Watch the “Privileged ISA” RISC-V Barcelona Workshop Tutorial Presentation.
Allen Baum, CPU Architect at Esperanto Technologies, presented a tutorial on the RISC-V privileged ISA, including a discussion on privileged architecture needs, features, modes and use case profiles.
And follow Esperanto news!
Vector ISA Proposal Update @RISC-V Barcelona Workshop
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Vector ISA Tutorial @RISC-V Barcelona Workshop 2018
“Vector ISA” RISC-V Barcelona Workshop Tutorial Presentation.
Roger Espasa, Chief Architect at Esperanto Technologies, delivered a tutorial on basic semantics and operation of the vector extension, including new states, configuration, instruction encoding and inter-operation, and more.
And follow Esperanto news!
