Esperanto @ Design & Reuse IP SOC Conference 2018

Date

April 5,  2018

Venue

Hyatt Regency, 5101 Great America Parkway, Santa Clara, CA.

Esperanto Technologies Presents at Design & Reuse IP SOC Conference 2018

Panel: The promises and pitfalls of RISC-V, from SOC Design Perspective

  • RISC-V offers great promise: an open source, growing community that will free customers from a single supplier solution. But that isn’t the whole story. Until now, the architecture was at the center of the SoC: Intel, ARM, MIPS. IP vendors picked (or developed) an architecture and fought each other on that basis. The customer “adopted” a vendor’s ISA first, then selected from the cores available from that vendor. Software might be written in C, but was also optimized for a proprietary language and not portable.
  • Today, cores are selected for what they do for the total design. Can a core solve or improve a system level problem? Is there a marketing advantage to use ARM or RISC-V? What IP surrounds the core and what software runs on the core drives the decision process. And most importantly, most software is written in C.

Organizer : Jonah McLeod, Andes Technology
Moderator : Kevin Krewell, Principal Analyst, TIRIAS Research
Panelists :

  • Art Swift, VP Marketing, Esperanto Technologies
  • Ted Speers, Product Architecture and Planning Head, Microsemi
  • Naveed Sherwani, President & CEO, SiFive
  • Emerson Hsiao, Senior VP, Andes Technology

Watch the videos of the panel here:

2018-08-13T06:30:04+00:00