RISC-V Global Event Series - Highlights Including comments from Celeste Cooper, Chief of Staff, Office of the CTO, at Western Digital.
JOIN THE RISC-V REVOLUTION! Attend the RISC-V Summit and be part of the disruptive force transforming the microprocessor IP market through open standard collaboration. Learn more about RISC-V. December 3 - 5, 2018 Santa Clara Convention Center, Santa Clara, CA Register Here [...]
Date June 24 - June 28, 2018 Venue Moscone Convention Center. San Francisco, CA. Visit the RISC-V Foundation booth in West Hall, level two, booth #2638. Esperanto Technologies is a proud leading member of the RISC-V Foundation! For more information, see the [...]
Hear Dave Patterson’s keynote @55thDAC: “A New Golden Age for Computer Architecture: Domain Specific Accelerators and Open RISC-V” When: June 27, 9:20 AM. Where: DAC 2018, Moscone Center, San Francisco, CA. Room 3008 For more information: click here. And follow Esperanto news! Twitter @EsperantoTech LinkedIn YouTube [...]
Meet Mike Dierickx of Esperanto Technologies at DAC 2018 Advancing Custom/AMS Design & Verification for Storage, Automotive, and AI Applications: a Synopsys Lunch Panel. Abstract: New-age applications such as storage, automotive, and AI are generating exacting demands on underlying semiconductor electronics such as Flash [...]
“Vector ISA” RISC-V Barcelona Workshop Tutorial Presentation. Roger Espasa, Chief Architect at Esperanto Technologies, delivered a tutorial on basic semantics and operation of the vector extension, including new states, configuration, instruction encoding and inter-operation, and more.
Christopher Celio and Jose Renau, CPU Architects from Esperanto Technologies, discussed potential changes to future high-performance RISC-V processors intended to eliminate speculation-based timing attacks, such as Spectre and Meltdown. They presented a proposal for RISC-V cores which minimizes changes to the RISC-V ISA or [...]
Roger Espasa, Chief Architect at Esperanto Technologies, presented a summary of the latest updates to the Vector ISA specification for the wider audience.