Date June 24 - June 28, 2018 Venue Moscone Convention Center. San Francisco, CA. Visit the RISC-V Foundation booth in West Hall, level two, booth #2638. Esperanto Technologies is a proud leading member of the RISC-V Foundation! For more information, see the [...]
Hear Dave Patterson’s keynote @55thDAC: “A New Golden Age for Computer Architecture: Domain Specific Accelerators and Open RISC-V” When: June 27, 9:20 AM. Where: DAC 2018, Moscone Center, San Francisco, CA. Room 3008 For more information: click here. And follow Esperanto news! Twitter @EsperantoTech LinkedIn YouTube [...]
Meet Mike Dierickx of Esperanto Technologies at DAC 2018 Advancing Custom/AMS Design & Verification for Storage, Automotive, and AI Applications: a Synopsys Lunch Panel. Abstract: New-age applications such as storage, automotive, and AI are generating exacting demands on underlying semiconductor electronics such as Flash [...]
“Vector ISA” RISC-V Barcelona Workshop Tutorial Presentation. Roger Espasa, Chief Architect at Esperanto Technologies, delivered a tutorial on basic semantics and operation of the vector extension, including new states, configuration, instruction encoding and inter-operation, and more.
Christopher Celio and Jose Renau, CPU Architects from Esperanto Technologies, discussed potential changes to future high-performance RISC-V processors intended to eliminate speculation-based timing attacks, such as Spectre and Meltdown. They presented a proposal for RISC-V cores which minimizes changes to the RISC-V ISA or [...]
Roger Espasa, Chief Architect at Esperanto Technologies, presented a summary of the latest updates to the Vector ISA specification for the wider audience.
Watch the “Privileged ISA” RISC-V Barcelona Workshop Tutorial Presentation. Allen Baum, CPU Architect at Esperanto Technologies, presented a tutorial on the RISC-V privileged ISA, including a discussion on privileged architecture needs, features, modes and use case profiles.
In Sensors Online. Esperanto has licensed NetSpeed's IP and intelligent design environment for its Supercomputer-on-a-Chip for artificial intelligence (AI) applications. Esperanto's 7-nm chip will integrate thousands of RISC-V compatible processors each with vector/tensor accelerators and all connected with NetSpeed's NoC IP. AI applications demand new [...]
In eeNews by Peter Clarke.Startup processor developer Esperanto Technologies Inc. (Mountain View, Calif.) is making use of the analytics IP from UltraSoC Ltd. (Cambridge, England) within its artificial intelligence chip that is projected to contain more than 4,000 64bit processor cores on 7nm manufacturing technology.Dave Ditzel, [...]