December 3-5, 2018
Santa Clara Convention Center, Santa Clara, CA.
JOIN THE RISC-V REVOLUTION
See Esperanto Technologies at the Inaugural RISC-V Summit, December 2018
Esperanto is sponsoring the RISC-V Summit, will deliver a processor technology paper, and invites you to “Join the RISC-V Revolution!” to be part of the disruptive force transforming the microprocessor IP market through open standard collaboration.
- What: RISC-V Summit.
- Where: Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, California.
- When: Conference and Exhibition Dec. 4-5. Pre-Conference Day Dec. 3. RISC-V Foundation Members Meeting Dec. 6.
- Agenda: View the agenda here.
The RISC-V Summit 2018 will feature an Esperanto exhibit, as well as a technology presentation on a RISC-V based processor design. Please contact email@example.com to set up a meeting.
- Authors: Polychronis Xekalakis and Chris Celio, CPU Architects at Esperanto Technologies.
- This talk presents an update on ET-Maxion, a high frequency out-of-order RISC-V core which is being designed for TSMC’s 7nm process. It describes the key micro-architectural features that allow ET-Maxion to achieve performance levels comparable to existing commercial high-end processors, and discusses design choices, including shielding against timing attacks such as Spectre and Meltdown, with negligible performance sacrifices. Experiences in implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, along with design challenges, are shared. Finally, a brief overview of support for post-silicon debug and planned performance monitoring improvements for ET-Maxion.
- Read more: See the complete presentation abstract here.
About the RISC-V Summit
The first annual Summit is a major international event promoting RISC-V, bringing together the community for a multi-track conference, tutorials, and exhibits, organized by the RISC-V Foundation, in partnership with Informa’s Knowledge & Networking Division, KNect365. For more information, see https://tmt.knect365.com/risc-v-summit/ For more information about RISC-V (pronounced “risk-five”), please see https://riscv.org.